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| author |  Adam Greig <adam@adamgreig.com>
| 2017-06-14 23:47:33 +0100 |
|---|---|---|
| committer | Adam Greig <adam@adamgreig.com>
| 2017-06-15 00:11:44 +0100 |
| commit | aa3e5d04305db00101967bca330956b13162faa6 (patch) | |
| tree | 61f620059a3424a749941af4c80b37eede6c2a5c | |
| parent | 45896618a3d012811015ec265cfb512c8d6458eb (diff) | |
| download | cortex-m-aa3e5d04305db00101967bca330956b13162faa6.tar.gz cortex-m-aa3e5d04305db00101967bca330956b13162faa6.tar.zst cortex-m-aa3e5d04305db00101967bca330956b13162faa6.zip | |
Add documentation note about set and way masking for CBP methods
| -rw-r--r-- | src/peripheral/mod.rs | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/peripheral/mod.rs b/src/peripheral/mod.rs index 235dbe3..d04a320 100644 --- a/src/peripheral/mod.rs +++ b/src/peripheral/mod.rs @@ -1005,6 +1005,8 @@ impl Cbp { } /// D-cache invalidate by set-way + /// + /// `set` is masked to be between 0 and 3, and `way` between 0 and 511. #[inline(always)] pub fn dcisw(&self, set: u16, way: u16) { // The ARMv7-M Architecture Reference Manual, as of Revision E.b, says these set/way @@ -1035,6 +1037,8 @@ impl Cbp { } /// D-cache clean by set-way + /// + /// `set` is masked to be between 0 and 3, and `way` between 0 and 511. #[inline(always)] pub fn dccsw(&self, set: u16, way: u16) { // See comment for dcisw() about the format here @@ -1051,6 +1055,8 @@ impl Cbp { } /// D-cache clean and invalidate by set-way + /// + /// `set` is masked to be between 0 and 3, and `way` between 0 and 511. #[inline(always)] pub fn dccisw(&self, set: u16, way: u16) { // See comment for dcisw() about the format here |