diff options
author | 2021-02-09 10:21:38 +0200 | |
---|---|---|
committer | 2021-02-09 10:21:38 +0200 | |
commit | 7b66016c1d680f78f56403c056dbe6ca3ebc0e23 (patch) | |
tree | e6ac3538ad1cab479964fd82a37305923c6c28b2 /asm/inline.rs | |
parent | 66955af9e80efcf4f54f178cd921186eb969f471 (diff) | |
download | cortex-m-7b66016c1d680f78f56403c056dbe6ca3ebc0e23.tar.gz cortex-m-7b66016c1d680f78f56403c056dbe6ca3ebc0e23.tar.zst cortex-m-7b66016c1d680f78f56403c056dbe6ca3ebc0e23.zip |
Extra comment
Diffstat (limited to 'asm/inline.rs')
-rw-r--r-- | asm/inline.rs | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/asm/inline.rs b/asm/inline.rs index a7898c5..5887baf 100644 --- a/asm/inline.rs +++ b/asm/inline.rs @@ -55,6 +55,7 @@ pub unsafe fn __delay(cyc: u32) { // The loop will normally take 3 to 4 CPU cycles per iteration, but superscalar cores // (eg. Cortex-M7) can potentially do it in 2, so we use that as the lower bound, since delaying // for more cycles is okay. + // Add 1 to prevent an integer underflow which would cause a long freeze let real_cyc = 1 + cyc / 2; asm!( // Use local labels to avoid R_ARM_THM_JUMP8 relocations which fail on thumbv6m. |