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| author |  Ovidiu Sabou <ovidiu@sabou.org>
| 2021-02-08 23:00:39 +0200 |
|---|---|---|
| committer | Ovidiu Sabou <ovidiu@sabou.org>
| 2021-02-08 23:29:56 +0200 |
| commit | a2edb2250059b9563a78c3bd00a52ceaee4f063f (patch) | |
| tree | f765c1ebc859288453db6dd03bb38814fe2b0f21 /asm/inline.rs | |
| parent | c714cdf20e012280a5c722d190a121a6bce10ddc (diff) | |
| download | cortex-m-a2edb2250059b9563a78c3bd00a52ceaee4f063f.tar.gz cortex-m-a2edb2250059b9563a78c3bd00a52ceaee4f063f.tar.zst cortex-m-a2edb2250059b9563a78c3bd00a52ceaee4f063f.zip | |
Prevent underflow when calling delay(n) with n<2
Calling delay(1) causes a very long wait (freeze) otherwise.
86cd463788b97ca3894936101c6cf4f3512f0fbc introduced this behaviour by
changing the cycle count from n / 4 + 1 to n / 2 which forces an
underflow when n<2.
Diffstat (limited to 'asm/inline.rs')
| -rw-r--r-- | asm/inline.rs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/asm/inline.rs b/asm/inline.rs index ef203cd..a7898c5 100644 --- a/asm/inline.rs +++ b/asm/inline.rs @@ -55,7 +55,7 @@ pub unsafe fn __delay(cyc: u32) { // The loop will normally take 3 to 4 CPU cycles per iteration, but superscalar cores // (eg. Cortex-M7) can potentially do it in 2, so we use that as the lower bound, since delaying // for more cycles is okay. - let real_cyc = cyc / 2; + let real_cyc = 1 + cyc / 2; asm!( // Use local labels to avoid R_ARM_THM_JUMP8 relocations which fail on thumbv6m. "1:", |