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authorGravatar bors[bot] <26634292+bors[bot]@users.noreply.github.com> 2020-07-12 22:11:38 +0000
committerGravatar GitHub <noreply@github.com> 2020-07-12 22:11:38 +0000
commit89832a7e1d467e75ac6093fe9560fd1dec65c51f (patch)
tree3ac62820ab4ee3d0c27078351670165f140e6e71 /cortex-m-rt/tests/compile-fail/unsafe-init-static.rs
parentfbcfff1a47cdba9c137d8b752f127f8efbfe7373 (diff)
parentcdc02c64d92bb7fdc8efb5e66c67f90c1dc8ec94 (diff)
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Merge #279
279: Add barriers after FPU enabling r=adamgreig a=thalesfragoso This only seems to be required for M7 cores, but since we can't know the specific core, we can't filter on that. I thought about using the SCB's `RegisterBlock` from cortex-m to enable the FPU, but the [registers](https://docs.rs/cortex-m/0.6.2/cortex_m/peripheral/scb/struct.RegisterBlock.html) are just the generics `RW` which isn't that different from what we're doing right now, and we would need `Peripherals::steal` to use the methods from SCB which would set the `CORE_PERIPHERALS`/`TAKEN` flag. And one question, with this change, can we get rid of the `trampoline()` function? I don't think the compiler will do reordering across foreign functions calls (dsb/isb), but I might be missing something. Co-authored-by: Thales Fragoso <thales.fragosoz@gmail.com>
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