diff options
| -rw-r--r-- | .travis.yml | 4 | ||||
| -rw-r--r-- | CHANGELOG.md | 4 | ||||
| -rw-r--r-- | build.rs | 1 | ||||
| -rw-r--r-- | ci/script.sh | 9 | ||||
| -rw-r--r-- | src/lib.rs | 1 | ||||
| -rw-r--r-- | src/macros.rs | 4 | ||||
| -rw-r--r-- | src/peripheral/dwt.rs | 2 | ||||
| -rw-r--r-- | src/peripheral/mod.rs | 1 | ||||
| -rw-r--r-- | src/peripheral/nvic.rs | 4 | ||||
| -rw-r--r-- | src/peripheral/scb.rs | 4 | ||||
| -rw-r--r-- | src/register/mod.rs | 27 |
11 files changed, 49 insertions, 12 deletions
diff --git a/.travis.yml b/.travis.yml index 1497c7a..64ba50b 100644 --- a/.travis.yml +++ b/.travis.yml @@ -62,6 +62,10 @@ matrix: rust: nightly if: (branch = staging OR branch = trying) OR (type = pull_request AND branch = master) + - env: TARGET=thumbv8m.base-none-eabi + rust: nightly + if: (branch = staging OR branch = trying) OR (type = pull_request AND branch = master) + before_install: set -e install: diff --git a/CHANGELOG.md b/CHANGELOG.md index 1d44da6..c4a4a2d 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] +### Deprecation + +- Deprecated incorrectly included registers (`BASPRI`, `BASEPRI_MAX`, `FAULTMASK`) on `thumbv8.base` + ## [v0.6.1] - 2019-08-21 ### Fixed @@ -29,6 +29,7 @@ fn main() { } else if target.starts_with("thumbv8m.base") { println!("cargo:rustc-cfg=cortex_m"); println!("cargo:rustc-cfg=armv8m"); + println!("cargo:rustc-cfg=armv8m_base"); } else if target.starts_with("thumbv8m.main") { println!("cargo:rustc-cfg=cortex_m"); println!("cargo:rustc-cfg=armv8m"); diff --git a/ci/script.sh b/ci/script.sh index 8046774..7c30993 100644 --- a/ci/script.sh +++ b/ci/script.sh @@ -31,6 +31,15 @@ main() { if [ $TARGET = x86_64-unknown-linux-gnu ]; then ./check-blobs.sh fi + + if [ $TRAVIS_RUST_VERSION = nightly ]; then + # Get the latest nightly with a working clippy + rustup toolchain uninstall nightly + rustup set profile default + rustup default nightly + rustup target add $TARGET + cargo clippy --target $TARGET -- -D warnings + fi } main @@ -33,6 +33,7 @@ #![deny(missing_docs)] #![no_std] #![allow(clippy::identity_op)] +#![allow(clippy::missing_safety_doc)] extern crate aligned; extern crate bare_metal; diff --git a/src/macros.rs b/src/macros.rs index 6b3b269..b578370 100644 --- a/src/macros.rs +++ b/src/macros.rs @@ -78,8 +78,6 @@ macro_rules! singleton { /// ``` compile_fail /// use cortex_m::singleton; /// -/// fn main() {} -/// /// fn foo() { /// // check that the call to `uninitialized` requires unsafe /// singleton!(: u8 = std::mem::uninitialized()); @@ -92,8 +90,6 @@ const CFAIL: () = (); /// #![deny(unsafe_code)] /// use cortex_m::singleton; /// -/// fn main() {} -/// /// fn foo() { /// // check that calls to `singleton!` don't trip the `unsafe_code` lint /// singleton!(: u8 = 0); diff --git a/src/peripheral/dwt.rs b/src/peripheral/dwt.rs index b340597..043223a 100644 --- a/src/peripheral/dwt.rs +++ b/src/peripheral/dwt.rs @@ -85,6 +85,6 @@ impl DWT { #[inline] pub fn unlock() { // NOTE(unsafe) atomic write to a stateless, write-only register - unsafe { (*Self::ptr()).lar.write(0xC5ACCE55) } + unsafe { (*Self::ptr()).lar.write(0xC5AC_CE55) } } } diff --git a/src/peripheral/mod.rs b/src/peripheral/mod.rs index 3884942..8854830 100644 --- a/src/peripheral/mod.rs +++ b/src/peripheral/mod.rs @@ -1,3 +1,4 @@ +#![allow(clippy::needless_doctest_main)] //! Core peripherals //! //! # API diff --git a/src/peripheral/nvic.rs b/src/peripheral/nvic.rs index 1a33023..1ecfc6e 100644 --- a/src/peripheral/nvic.rs +++ b/src/peripheral/nvic.rs @@ -171,7 +171,7 @@ impl NVIC { { // NOTE(unsafe) atomic read with no side effects let ipr_n = unsafe { (*Self::ptr()).ipr[Self::ipr_index(&interrupt)].read() }; - let prio = (ipr_n >> Self::ipr_shift(&interrupt)) & 0x000000ff; + let prio = (ipr_n >> Self::ipr_shift(&interrupt)) & 0x0000_00ff; prio as u8 } } @@ -264,7 +264,7 @@ impl NVIC { #[cfg(armv6m)] { self.ipr[Self::ipr_index(&interrupt)].modify(|value| { - let mask = 0x000000ff << Self::ipr_shift(&interrupt); + let mask = 0x0000_00ff << Self::ipr_shift(&interrupt); let prio = u32::from(prio) << Self::ipr_shift(&interrupt); (value & !mask) | prio diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs index 3dfa110..0e2eefc 100644 --- a/src/peripheral/scb.rs +++ b/src/peripheral/scb.rs @@ -798,7 +798,7 @@ impl SCB { { // NOTE(unsafe) atomic read with no side effects let shpr = unsafe { (*Self::ptr()).shpr[usize::from((index - 8) / 4)].read() }; - let prio = (shpr >> (8 * (index % 4))) & 0x000000ff; + let prio = (shpr >> (8 * (index % 4))) & 0x0000_00ff; prio as u8 } } @@ -828,7 +828,7 @@ impl SCB { { self.shpr[usize::from((index - 8) / 4)].modify(|value| { let shift = 8 * (index % 4); - let mask = 0x000000ff << shift; + let mask = 0x0000_00ff << shift; let prio = u32::from(prio) << shift; (value & !mask) | prio diff --git a/src/register/mod.rs b/src/register/mod.rs index 854d725..e7879c5 100644 --- a/src/register/mod.rs +++ b/src/register/mod.rs @@ -26,15 +26,36 @@ //! //! - Cortex-M* Devices Generic User Guide - Section 2.1.3 Core registers -#[cfg(not(armv6m))] +#[cfg(all(not(armv6m), not(armv8m_base)))] pub mod basepri; -#[cfg(not(armv6m))] +#[cfg(armv8m_base)] +#[deprecated( + since = "0.6.2", + note = "basepri is unavailable on thumbv8.base, and will be removed in the next release" +)] +pub mod basepri; + +#[cfg(all(not(armv6m), not(armv8m_base)))] +pub mod basepri_max; + +#[cfg(armv8m_base)] +#[deprecated( + since = "0.6.2", + note = "basepri is unavailable on thumbv8m.base, and will be removed in the next release" +)] pub mod basepri_max; pub mod control; -#[cfg(not(armv6m))] +#[cfg(all(not(armv6m), not(armv8m_base)))] +pub mod faultmask; + +#[cfg(armv8m_base)] +#[deprecated( + since = "0.6.2", + note = "faultmask is unavailable on thumbv8m.base, and will be removed in the next release" +)] pub mod faultmask; pub mod msp; |