diff options
| -rw-r--r-- | .travis.yml | 4 | ||||
| -rw-r--r-- | Cargo.toml | 7 | ||||
| -rwxr-xr-x | assemble.sh | 3 | ||||
| -rw-r--r-- | bin/thumbv8m.main-none-eabi.a | bin | 0 -> 2720 bytes | |||
| -rw-r--r-- | src/itm.rs | 6 | ||||
| -rw-r--r-- | src/peripheral/scb.rs | 2 | ||||
| -rw-r--r-- | src/peripheral/test.rs | 2 |
7 files changed, 17 insertions, 7 deletions
diff --git a/.travis.yml b/.travis.yml index ac4b63c..1aead9b 100644 --- a/.travis.yml +++ b/.travis.yml @@ -38,6 +38,10 @@ matrix: rust: nightly if: (branch = staging OR branch = trying) OR (type = pull_request AND branch = master) + - env: TARGET=thumbv8m.main-none-eabi + rust: nightly + if: (branch = staging OR branch = trying) OR (type = pull_request AND branch = master) + before_install: set -e install: @@ -1,5 +1,8 @@ [package] -authors = ["Jorge Aparicio <jorge@japaric.io>"] +authors = [ + "The Cortex-M Team <cortex-m@teams.rust-embedded.org>", + "Jorge Aparicio <jorge@japaric.io>", +] categories = ["embedded", "hardware-support", "no-std"] description = "Low level access to Cortex-M processors" documentation = "https://docs.rs/cortex-m" @@ -11,7 +14,7 @@ repository = "https://github.com/japaric/cortex-m" version = "0.5.8" [dependencies] -aligned = "0.2.0" +aligned = "0.3.1" bare-metal = "0.2.0" volatile-register = "0.2.0" diff --git a/assemble.sh b/assemble.sh index f003f58..28494a9 100755 --- a/assemble.sh +++ b/assemble.sh @@ -25,6 +25,9 @@ ar crs bin/thumbv7em-none-eabihf.a bin/$crate.o bin/$crate-v7.o bin/$crate-cm7-r arm-none-eabi-as -march=armv8-m.base asm.s -o bin/$crate.o ar crs bin/thumbv8m.base-none-eabi.a bin/$crate.o +arm-none-eabi-as -march=armv8-m.main asm.s -o bin/$crate.o +ar crs bin/thumbv8m.main-none-eabi.a bin/$crate.o + rm bin/$crate.o rm bin/$crate-v7.o rm bin/$crate-cm7-r0p1.o diff --git a/bin/thumbv8m.main-none-eabi.a b/bin/thumbv8m.main-none-eabi.a Binary files differnew file mode 100644 index 0000000..6dddb2e --- /dev/null +++ b/bin/thumbv8m.main-none-eabi.a @@ -4,7 +4,7 @@ use core::{fmt, mem, ptr, slice}; -use aligned::Aligned; +use aligned::{Aligned, A4}; use peripheral::itm::Stim; @@ -77,7 +77,7 @@ pub fn write_all(port: &mut Stim, buffer: &[u8]) { /// # Examples /// /// ``` ignore -/// let mut buffer: Aligned<u32, _> = Aligned([0; 14]); +/// let mut buffer: Aligned<A4, _> = Aligned([0; 14]); /// /// buffer.copy_from_slice(b"Hello, world!\n"); /// @@ -86,7 +86,7 @@ pub fn write_all(port: &mut Stim, buffer: &[u8]) { /// // Or equivalently /// itm::write_aligned(&itm.stim[0], &Aligned(*b"Hello, world!\n")); /// ``` -pub fn write_aligned(port: &mut Stim, buffer: &Aligned<u32, [u8]>) { +pub fn write_aligned(port: &mut Stim, buffer: &Aligned<A4, [u8]>) { unsafe { let len = buffer.len(); diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs index 4bf9270..c82e098 100644 --- a/src/peripheral/scb.rs +++ b/src/peripheral/scb.rs @@ -48,7 +48,7 @@ pub struct RegisterBlock { pub shpr: [RW<u32>; 2], /// System Handler Control and State - pub shcrs: RW<u32>, + pub shcsr: RW<u32>, /// Configurable Fault Status (not present on Cortex-M0 variants) #[cfg(not(armv6m))] diff --git a/src/peripheral/test.rs b/src/peripheral/test.rs index 5c6ce2d..d0d713a 100644 --- a/src/peripheral/test.rs +++ b/src/peripheral/test.rs @@ -129,7 +129,7 @@ fn scb() { assert_eq!(address(&scb.scr), 0xE000_ED10); assert_eq!(address(&scb.ccr), 0xE000_ED14); assert_eq!(address(&scb.shpr), 0xE000_ED18); - assert_eq!(address(&scb.shcrs), 0xE000_ED24); + assert_eq!(address(&scb.shcsr), 0xE000_ED24); assert_eq!(address(&scb.cfsr), 0xE000_ED28); assert_eq!(address(&scb.hfsr), 0xE000_ED2C); assert_eq!(address(&scb.dfsr), 0xE000_ED30); |