diff options
| -rw-r--r-- | CHANGELOG.md | 11 | ||||
| -rw-r--r-- | src/lib.rs | 1 |
2 files changed, 10 insertions, 2 deletions
diff --git a/CHANGELOG.md b/CHANGELOG.md index ec96200..4e2b1bd 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] +## [v0.3.0] - 2017-07-07 + ### Changed - [breaking-change] Renamed `StackedRergisters` to `ExceptionFrame` to better @@ -18,6 +20,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/). - [breaking-change] Renamed `Exception::current` to `Exception::active` and changed the signature to return `None` when no exception is being serviced. +- Moved bits non specific to the Cortex-M architecture into the [`bare-metal`] + crate with the goal of sharing code between this crate and crates tailored for + other (microcontroller) architectures. + +[`bare-metal`]: https://crates.io/crates/bare-metal + ### Removed - [breaking-change] The `ctxt` module along with the exception "tokens" in the @@ -337,7 +345,8 @@ fn main() { - Functions to get the vector table - Wrappers over miscellaneous instructions like `bkpt` -[Unreleased]: https://github.com/japaric/cortex-m/compare/v0.2.11...HEAD +[Unreleased]: https://github.com/japaric/cortex-m/compare/v0.3.0...HEAD +[v0.3.0]: https://github.com/japaric/cortex-m/compare/v0.2.11...v0.3.0 [v0.2.11]: https://github.com/japaric/cortex-m/compare/v0.2.10...v0.2.11 [v0.2.10]: https://github.com/japaric/cortex-m/compare/v0.2.9...v0.2.10 [v0.2.9]: https://github.com/japaric/cortex-m/compare/v0.2.8...v0.2.9 @@ -5,7 +5,6 @@ //! - Access to core peripherals like NVIC, SCB and SysTick. //! - Access to core registers like CONTROL, MSP and PSR. //! - Interrupt manipulation mechanisms -//! - Data structures like the vector table //! - Safe wrappers around assembly instructions like `bkpt` #![deny(missing_docs)] |