diff options
| -rw-r--r-- | CHANGELOG.md | 34 | ||||
| -rw-r--r-- | Cargo.toml | 2 |
2 files changed, 26 insertions, 10 deletions
diff --git a/CHANGELOG.md b/CHANGELOG.md index 8f3ad1e..c1e61b6 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -8,6 +8,18 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] ### Added +- Updated `SCB.ICSR.VECTACTIVE`/`SCB::vect_active()` to be 9 bits instead of 8. + Also fixes `VectActive::from` to take a `u16` and subtract `16` for + `VectActive::Interrupt`s to match `SBC::vect_active()` (#373). +- DWT: add `configure` API for address, cycle count comparison (#342, #367). +- ITM: add `configure` API (#342). +- TPIU: add API for *Formatter and Flush Control* (FFCR) and *Selected Pin Control* (SPPR) registers (#342). +- Add `std` and `serde` crate features for improved host-side ITM decode functionality when working with the downstream `itm`, `cargo-rtic-scope` crates (#363, #366). + +## [v0.7.4] - 2021-12-31 + +### Added + - Added support for additional DWT counters (#349) - CPI counter - Exception overhead counter @@ -15,16 +27,18 @@ and this project adheres to [Semantic Versioning](http://semver.org/). - Folded-instruction counter - Added `DWT.set_cycle_count` (#347). - Added support for the Cortex-M7 TCM and cache access control registers. - There is a feature `cm7` to enable access to these. + There is a feature `cm7` to enable access to these (#352). +- Add derives for serde, Hash, and PartialOrd to VectActive behind feature + gates for host-platform use (#363). +- Support host platforms besides x86_64 (#369). - Added `delay::Delay::with_source`, a constructor that lets you specify the SysTick clock source (#374). -- Updated `SCB.ICSR.VECTACTIVE`/`SCB::vect_active()` to be 9 bits instead of 8. - Also fixes `VectActive::from` to take a `u16` and subtract `16` for - `VectActive::Interrupt`s to match `SBC::vect_active()` (#373). -- DWT: add `configure` API for address, cycle count comparison (#342, #367). -- ITM: add `configure` API (#342). -- TPIU: add API for *Formatter and Flush Control* (FFCR) and *Selected Pin Control* (SPPR) registers (#342). -- Add `std` and `serde` crate features for improved host-side ITM decode functionality when working with the downstream `itm`, `cargo-rtic-scope` crates (#363, #366). + +### Fixed + +- Fix incorrect AIRCR PRIGROUP mask (#338, #339). +- Fix nightly users of inline-asm breaking now that the asm macro is removed + from the prelude (#372). ### Deprecated @@ -33,6 +47,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). [C-GETTER]: https://rust-lang.github.io/api-guidelines/naming.html#c-getter + ## [v0.7.3] - 2021-07-03 ### Fixed @@ -726,7 +741,8 @@ fn main() { - Functions to get the vector table - Wrappers over miscellaneous instructions like `bkpt` -[Unreleased]: https://github.com/rust-embedded/cortex-m/compare/v0.7.3...HEAD +[Unreleased]: https://github.com/rust-embedded/cortex-m/compare/v0.7.4...HEAD +[v0.7.4]: https://github.com/rust-embedded/cortex-m/compare/v0.7.3...v0.7.4 [v0.7.3]: https://github.com/rust-embedded/cortex-m/compare/v0.7.2...v0.7.3 [v0.7.2]: https://github.com/rust-embedded/cortex-m/compare/v0.7.1...v0.7.2 [v0.7.1]: https://github.com/rust-embedded/cortex-m/compare/v0.7.0...v0.7.1 @@ -11,7 +11,7 @@ license = "MIT OR Apache-2.0" name = "cortex-m" readme = "README.md" repository = "https://github.com/rust-embedded/cortex-m" -version = "0.7.3" +version = "0.7.4" edition = "2018" links = "cortex-m" # prevent multiple versions of this crate to be linked together |