13 files changed, 144 insertions, 16 deletions
diff --git a/.travis.yml b/.travis.yml
index ac4b63c..1aead9b 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -38,6 +38,10 @@ matrix:
       rust: nightly
       if: (branch = staging OR branch = trying) OR (type = pull_request AND branch = master)
 
+    - env: TARGET=thumbv8m.main-none-eabi
+      rust: nightly
+      if: (branch = staging OR branch = trying) OR (type = pull_request AND branch = master)
+
 before_install: set -e
 
 install:
diff --git a/CHANGELOG.md b/CHANGELOG.md
index f265594..cf1e370 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -7,6 +7,23 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.6.0] - 2019-03-12
+
+### Fixed
+
+- Fix numerous registers which were incorrectly included for thumbv6
+- `SHCRS` renamed to `SHCSR` in `SCB`
+
+### Added
+
+- Support for ARMv8-M (`thumbv8.base` and `thumbv8.main`)
+
+- `SCB` gained methods to set and clear `SLEEPONEXIT` bit
+
+- `NVIC` gained `STIR` register and methods to request an interrupt
+
+- `DCB` gained methods to check if debugger is attached
+
 ## [v0.5.8] - 2018-10-27
 
 ### Added
@@ -529,7 +546,8 @@ fn main() {
 - Functions to get the vector table
 - Wrappers over miscellaneous instructions like `bkpt`
 
-[Unreleased]: https://github.com/rust-embedded/cortex-m/compare/v0.5.8...HEAD
+[Unreleased]: https://github.com/rust-embedded/cortex-m/compare/v0.6.0...HEAD
+[v0.6.0]: https://github.com/rust-embedded/cortex-m/compare/v0.5.8...v0.6.0
 [v0.5.8]: https://github.com/rust-embedded/cortex-m/compare/v0.5.7...v0.5.8
 [v0.5.7]: https://github.com/rust-embedded/cortex-m/compare/v0.5.6...v0.5.7
 [v0.5.6]: https://github.com/rust-embedded/cortex-m/compare/v0.5.5...v0.5.6
diff --git a/Cargo.toml b/Cargo.toml
index cf46c29..01d5911 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -1,5 +1,8 @@
 [package]
-authors = ["Jorge Aparicio <jorge@japaric.io>"]
+authors = [
+    "The Cortex-M Team <cortex-m@teams.rust-embedded.org>",
+    "Jorge Aparicio <jorge@japaric.io>",
+]
 categories = ["embedded", "hardware-support", "no-std"]
 description = "Low level access to Cortex-M processors"
 documentation = "https://docs.rs/cortex-m"
@@ -8,10 +11,10 @@ license = "MIT OR Apache-2.0"
 name = "cortex-m"
 readme = "README.md"
 repository = "https://github.com/japaric/cortex-m"
-version = "0.5.8"
+version = "0.6.0"
 
 [dependencies]
-aligned = "0.2.0"
+aligned = "0.3.1"
 bare-metal = "0.2.0"
 volatile-register = "0.2.0"
 
diff --git a/assemble.sh b/assemble.sh
index d1e743b..28494a9 100755
--- a/assemble.sh
+++ b/assemble.sh
@@ -22,6 +22,12 @@ arm-none-eabi-as -march=armv7e-m asm-cm7-r0p1.s -o bin/$crate-cm7-r0p1.o
 ar crs bin/thumbv7em-none-eabi.a bin/$crate.o bin/$crate-v7.o bin/$crate-cm7-r0p1.o
 ar crs bin/thumbv7em-none-eabihf.a bin/$crate.o bin/$crate-v7.o bin/$crate-cm7-r0p1.o
 
+arm-none-eabi-as -march=armv8-m.base asm.s -o bin/$crate.o
+ar crs bin/thumbv8m.base-none-eabi.a bin/$crate.o
+
+arm-none-eabi-as -march=armv8-m.main asm.s -o bin/$crate.o
+ar crs bin/thumbv8m.main-none-eabi.a bin/$crate.o
+
 rm bin/$crate.o
 rm bin/$crate-v7.o
 rm bin/$crate-cm7-r0p1.o
diff --git a/bin/thumbv8m.base-none-eabi.a b/bin/thumbv8m.base-none-eabi.a
new file mode 100644
index 0000000..6c6ce41
--- /dev/null
+++ b/bin/thumbv8m.base-none-eabi.a
diff --git a/bin/thumbv8m.main-none-eabi.a b/bin/thumbv8m.main-none-eabi.a
new file mode 100644
index 0000000..6dddb2e
--- /dev/null
+++ b/bin/thumbv8m.main-none-eabi.a
diff --git a/build.rs b/build.rs
index 6d08ba9..47e86bb 100644
--- a/build.rs
+++ b/build.rs
@@ -26,6 +26,9 @@ fn main() {
         println!("cargo:rustc-cfg=cortex_m");
         println!("cargo:rustc-cfg=armv7m");
         //println!("cargo:rustc-cfg=armv7em");
+    } else if target.starts_with("thumbv8m") {
+        println!("cargo:rustc-cfg=cortex_m");
+        println!("cargo:rustc-cfg=armv8m");
     }
 
     if target.ends_with("-eabihf") {
diff --git a/src/itm.rs b/src/itm.rs
index 0e32e3c..4f8dcf8 100644
--- a/src/itm.rs
+++ b/src/itm.rs
@@ -4,7 +4,7 @@
 
 use core::{fmt, mem, ptr, slice};
 
-use aligned::Aligned;
+use aligned::{Aligned, A4};
 
 use peripheral::itm::Stim;
 
@@ -77,7 +77,7 @@ pub fn write_all(port: &mut Stim, buffer: &[u8]) {
 /// # Examples
 ///
 /// ``` ignore
-/// let mut buffer: Aligned<u32, _> = Aligned([0; 14]);
+/// let mut buffer: Aligned<A4, _> = Aligned([0; 14]);
 ///
 /// buffer.copy_from_slice(b"Hello, world!\n");
 ///
@@ -86,7 +86,7 @@ pub fn write_all(port: &mut Stim, buffer: &[u8]) {
 /// // Or equivalently
 /// itm::write_aligned(&itm.stim[0], &Aligned(*b"Hello, world!\n"));
 /// ```
-pub fn write_aligned(port: &mut Stim, buffer: &Aligned<u32, [u8]>) {
+pub fn write_aligned(port: &mut Stim, buffer: &Aligned<A4, [u8]>) {
     unsafe {
         let len = buffer.len();
 
diff --git a/src/peripheral/dcb.rs b/src/peripheral/dcb.rs
index 14dc75b..e12542c 100644
--- a/src/peripheral/dcb.rs
+++ b/src/peripheral/dcb.rs
@@ -2,6 +2,7 @@
 
 use volatile_register::{RW, WO};
 
+use core::ptr;
 use peripheral::DCB;
 
 const DCB_DEMCR_TRCENA: u32 = 1 << 24;
@@ -20,18 +21,37 @@ pub struct RegisterBlock {
 }
 
 impl DCB {
-    /// Enables TRACE. This is for example required by the 
+    /// Enables TRACE. This is for example required by the
     /// `peripheral::DWT` cycle counter to work properly.
     /// As by STM documentation, this flag is not reset on
     /// soft-reset, only on power reset.
     pub fn enable_trace(&mut self) {
         // set bit 24 / TRCENA
-        unsafe { self.demcr.modify(|w| w | DCB_DEMCR_TRCENA); }
+        unsafe {
+            self.demcr.modify(|w| w | DCB_DEMCR_TRCENA);
+        }
     }
-    
+
     /// Disables TRACE. See `DCB::enable_trace()` for more details
     pub fn disable_trace(&mut self) {
         // unset bit 24 / TRCENA
-        unsafe { self.demcr.modify(|w| w & !DCB_DEMCR_TRCENA); }
+        unsafe {
+            self.demcr.modify(|w| w & !DCB_DEMCR_TRCENA);
+        }
+    }
+
+    /// Is there a debugger attached? (see note)
+    ///
+    /// Note: This function is [reported not to
+    /// work](http://web.archive.org/web/20180821191012/https://community.nxp.com/thread/424925#comment-782843)
+    /// on Cortex-M0 devices. Per the ARM v6-M Architecture Reference Manual, "Access to the DHCSR
+    /// from software running on the processor is IMPLEMENTATION DEFINED". Indeed, from the
+    /// [Cortex-M0+ r0p1 Technical Reference Manual](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0484c/BABJHEIG.html), "Note Software cannot access the debug registers."
+    pub fn is_debugger_attached() -> bool {
+        unsafe {
+            // do an 8-bit read of the 32-bit DHCSR register, and get the LSB
+            let value = ptr::read_volatile(Self::ptr() as *const u8);
+            value & 0x1 == 1
+        }
     }
 }
diff --git a/src/peripheral/dwt.rs b/src/peripheral/dwt.rs
index 84f002e..77ec450 100644
--- a/src/peripheral/dwt.rs
+++ b/src/peripheral/dwt.rs
@@ -1,6 +1,8 @@
 //! Data Watchpoint and Trace unit
 
-use volatile_register::{RO, RW, WO};
+#[cfg(not(armv6m))]
+use volatile_register::WO;
+use volatile_register::{RO, RW};
 
 use peripheral::DWT;
 
@@ -10,25 +12,41 @@ pub struct RegisterBlock {
     /// Control
     pub ctrl: RW<u32>,
     /// Cycle Count
+    #[cfg(not(armv6m))]
     pub cyccnt: RW<u32>,
     /// CPI Count
+    #[cfg(not(armv6m))]
     pub cpicnt: RW<u32>,
     /// Exception Overhead Count
+    #[cfg(not(armv6m))]
     pub exccnt: RW<u32>,
     /// Sleep Count
+    #[cfg(not(armv6m))]
     pub sleepcnt: RW<u32>,
     /// LSU Count
+    #[cfg(not(armv6m))]
     pub lsucnt: RW<u32>,
     /// Folded-instruction Count
+    #[cfg(not(armv6m))]
     pub foldcnt: RW<u32>,
+    /// Cortex-M0(+) does not have  these parts
+    #[cfg(armv6m)]
+    reserved: [u32; 6],
     /// Program Counter Sample
     pub pcsr: RO<u32>,
     /// Comparators
+    #[cfg(armv6m)]
+    pub c: [Comparator; 2],
+    #[cfg(not(armv6m))]
+    /// Comparators
     pub c: [Comparator; 16],
+    #[cfg(not(armv6m))]
     reserved: [u32; 932],
     /// Lock Access
+    #[cfg(not(armv6m))]
     pub lar: WO<u32>,
     /// Lock Status
+    #[cfg(not(armv6m))]
     pub lsr: RO<u32>,
 }
 
@@ -46,11 +64,13 @@ pub struct Comparator {
 
 impl DWT {
     /// Enables the cycle counter
+    #[cfg(not(armv6m))]
     pub fn enable_cycle_counter(&mut self) {
         unsafe { self.ctrl.modify(|r| r | 1) }
     }
 
     /// Returns the current clock cycle count
+    #[cfg(not(armv6m))]
     pub fn get_cycle_count() -> u32 {
         // NOTE(unsafe) atomic read with no side effects
         unsafe { (*Self::ptr()).cyccnt.read() }
diff --git a/src/peripheral/nvic.rs b/src/peripheral/nvic.rs
index c59c2c8..57ce009 100644
--- a/src/peripheral/nvic.rs
+++ b/src/peripheral/nvic.rs
@@ -1,8 +1,8 @@
 //! Nested Vector Interrupt Controller
 
-#[cfg(not(armv6m))]
-use volatile_register::RO;
 use volatile_register::RW;
+#[cfg(not(armv6m))]
+use volatile_register::{RO, WO};
 
 use interrupt::Nr;
 use peripheral::NVIC;
@@ -65,9 +65,35 @@ pub struct RegisterBlock {
     /// so convenient byte-sized representation wouldn't work on that
     /// architecture.
     pub ipr: [RW<u32>; 8],
+
+    #[cfg(not(armv6m))]
+    _reserved6: [u32; 580],
+
+    #[cfg(not(armv6m))]
+    /// Software Trigger Interrupt
+    pub stir: WO<u32>,
 }
 
 impl NVIC {
+    #[cfg(not(armv6m))]
+    /// Request an IRQ in software
+    ///
+    /// Writing a value to the INTID field is the same as manually pending an interrupt by setting
+    /// the corresponding interrupt bit in an Interrupt Set Pending Register. This is similar to
+    /// `set_pending`.
+    ///
+    /// This method is not available on ARMv6-M chips.
+    pub fn request<I>(&mut self, interrupt: I)
+    where
+        I: Nr,
+    {
+        let nr = interrupt.nr();
+
+        unsafe {
+            self.stir.write(nr as u32);
+        }
+    }
+
     /// Clears `interrupt`'s pending state
     #[deprecated(since = "0.5.8", note = "Use `NVIC::unpend`")]
     pub fn clear_pending<I>(&mut self, interrupt: I)
diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs
index b584941..59eedba 100644
--- a/src/peripheral/scb.rs
+++ b/src/peripheral/scb.rs
@@ -48,7 +48,7 @@ pub struct RegisterBlock {
     pub shpr: [RW<u32>; 2],
 
     /// System Handler Control and State
-    pub shcrs: RW<u32>,
+    pub shcsr: RW<u32>,
 
     /// Configurable Fault Status (not present on Cortex-M0 variants)
     #[cfg(not(armv6m))]
@@ -596,6 +596,24 @@ impl SCB {
     }
 }
 
+const SCB_SCR_SLEEPONEXIT: u32 = 0x1 << 1;
+
+impl SCB {
+    /// Set the SLEEPONEXIT bit in the SCR register
+    pub fn set_sleeponexit(&mut self) {
+        unsafe {
+            self.scr.modify(|scr| scr | SCB_SCR_SLEEPONEXIT);
+        }
+    }
+
+    /// Clear the SLEEPONEXIT bit in the SCR register
+    pub fn clear_sleeponexit(&mut self) {
+        unsafe {
+            self.scr.modify(|scr| scr & !SCB_SCR_SLEEPONEXIT);
+        }
+    }
+}
+
 const SCB_AIRCR_VECTKEY: u32 = 0x05FA << 16;
 const SCB_AIRCR_PRIGROUP_MASK: u32 = 0x5 << 8;
 const SCB_AIRCR_SYSRESETREQ: u32 = 1 << 2;
diff --git a/src/peripheral/test.rs b/src/peripheral/test.rs
index cc3e292..4eb48f5 100644
--- a/src/peripheral/test.rs
+++ b/src/peripheral/test.rs
@@ -29,11 +29,17 @@ fn dwt() {
     let dwt = unsafe { &*::peripheral::DWT::ptr() };
 
     assert_eq!(address(&dwt.ctrl), 0xE000_1000);
+    #[cfg(not(armv6m))]
     assert_eq!(address(&dwt.cyccnt), 0xE000_1004);
+    #[cfg(not(armv6m))]
     assert_eq!(address(&dwt.cpicnt), 0xE000_1008);
+    #[cfg(not(armv6m))]
     assert_eq!(address(&dwt.exccnt), 0xE000_100C);
+    #[cfg(not(armv6m))]
     assert_eq!(address(&dwt.sleepcnt), 0xE000_1010);
+    #[cfg(not(armv6m))]
     assert_eq!(address(&dwt.lsucnt), 0xE000_1014);
+    #[cfg(not(armv6m))]
     assert_eq!(address(&dwt.foldcnt), 0xE000_1018);
     assert_eq!(address(&dwt.pcsr), 0xE000_101C);
     assert_eq!(address(&dwt.c[0].comp), 0xE000_1020);
@@ -42,7 +48,9 @@ fn dwt() {
     assert_eq!(address(&dwt.c[1].comp), 0xE000_1030);
     assert_eq!(address(&dwt.c[1].mask), 0xE000_1034);
     assert_eq!(address(&dwt.c[1].function), 0xE000_1038);
+    #[cfg(not(armv6m))]
     assert_eq!(address(&dwt.lar), 0xE000_1FB0);
+    #[cfg(not(armv6m))]
     assert_eq!(address(&dwt.lsr), 0xE000_1FB4);
 }
 
@@ -109,6 +117,8 @@ fn nvic() {
     assert_eq!(address(&nvic.icpr), 0xE000E280);
     assert_eq!(address(&nvic.iabr), 0xE000E300);
     assert_eq!(address(&nvic.ipr), 0xE000E400);
+    #[cfg(not(armv6m))]
+    assert_eq!(address(&nvic.stir), 0xE000EF00);
 }
 
 #[test]
@@ -121,7 +131,7 @@ fn scb() {
     assert_eq!(address(&scb.scr), 0xE000_ED10);
     assert_eq!(address(&scb.ccr), 0xE000_ED14);
     assert_eq!(address(&scb.shpr), 0xE000_ED18);
-    assert_eq!(address(&scb.shcrs), 0xE000_ED24);
+    assert_eq!(address(&scb.shcsr), 0xE000_ED24);
     assert_eq!(address(&scb.cfsr), 0xE000_ED28);
     assert_eq!(address(&scb.hfsr), 0xE000_ED2C);
     assert_eq!(address(&scb.dfsr), 0xE000_ED30);