diff options
| -rw-r--r-- | src/lib.rs | 2 | ||||
| -rw-r--r-- | src/peripheral/cbp.rs | 2 | ||||
| -rw-r--r-- | src/peripheral/cpuid.rs | 16 | ||||
| -rw-r--r-- | src/peripheral/fpb.rs | 2 | ||||
| -rw-r--r-- | src/peripheral/fpu.rs | 7 | ||||
| -rw-r--r-- | src/peripheral/itm.rs | 2 | ||||
| -rw-r--r-- | src/peripheral/mod.rs | 79 | ||||
| -rw-r--r-- | src/peripheral/scb.rs | 12 | ||||
| -rw-r--r-- | src/peripheral/tpiu.rs | 2 |
9 files changed, 83 insertions, 41 deletions
@@ -24,6 +24,8 @@ mod macros; pub mod asm; pub mod exception; pub mod interrupt; +// NOTE(target_arch) is for documentation purposes +#[cfg(any(armv7m, target_arch = "x86_64"))] pub mod itm; pub mod peripheral; pub mod register; diff --git a/src/peripheral/cbp.rs b/src/peripheral/cbp.rs index 590cb7b..2535d0b 100644 --- a/src/peripheral/cbp.rs +++ b/src/peripheral/cbp.rs @@ -1,4 +1,6 @@ //! Cache and branch predictor maintenance operations +//! +//! *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`) use volatile_register::WO; diff --git a/src/peripheral/cpuid.rs b/src/peripheral/cpuid.rs index 624d5c5..94a2c20 100644 --- a/src/peripheral/cpuid.rs +++ b/src/peripheral/cpuid.rs @@ -1,10 +1,10 @@ //! CPUID use volatile_register::RO; -#[cfg(any(armv7m, test))] +#[cfg(any(armv7m, target_arch = "x86_64"))] use volatile_register::RW; -#[cfg(armv7m)] +#[cfg(any(armv7m, target_arch = "x86_64"))] use peripheral::CPUID; /// Register block @@ -25,21 +25,21 @@ pub struct RegisterBlock { pub isar: [RO<u32>; 5], reserved1: u32, /// Cache Level ID - #[cfg(any(armv7m, test))] + #[cfg(any(armv7m, target_arch = "x86_64"))] pub clidr: RO<u32>, /// Cache Type - #[cfg(any(armv7m, test))] + #[cfg(any(armv7m, target_arch = "x86_64"))] pub ctr: RO<u32>, /// Cache Size ID - #[cfg(any(armv7m, test))] + #[cfg(any(armv7m, target_arch = "x86_64"))] pub ccsidr: RO<u32>, /// Cache Size Selection - #[cfg(any(armv7m, test))] + #[cfg(any(armv7m, target_arch = "x86_64"))] pub csselr: RW<u32>, } /// Type of cache to select on CSSELR writes. -#[cfg(armv7m)] +#[cfg(any(armv7m, target_arch = "x86_64"))] pub enum CsselrCacheType { /// Select DCache or unified cache DataOrUnified = 0, @@ -47,7 +47,7 @@ pub enum CsselrCacheType { Instruction = 1, } -#[cfg(armv7m)] +#[cfg(any(armv7m, target_arch = "x86_64"))] impl CPUID { /// Selects the current CCSIDR /// diff --git a/src/peripheral/fpb.rs b/src/peripheral/fpb.rs index 0da2d5d..215d4ff 100644 --- a/src/peripheral/fpb.rs +++ b/src/peripheral/fpb.rs @@ -1,4 +1,6 @@ //! Flash Patch and Breakpoint unit +//! +//! *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`) use volatile_register::{RO, RW, WO}; diff --git a/src/peripheral/fpu.rs b/src/peripheral/fpu.rs index ada8b7a..c4e8a1d 100644 --- a/src/peripheral/fpu.rs +++ b/src/peripheral/fpu.rs @@ -1,6 +1,7 @@ //! Floating Point Unit +//! +//! *NOTE* Available only on ARMv7E-M (`thumbv7em-none-eabihf`) -#[cfg(any(has_fpu, test))] use volatile_register::{RO, RW}; /// Register block @@ -8,15 +9,11 @@ use volatile_register::{RO, RW}; pub struct RegisterBlock { reserved: u32, /// Floating Point Context Control - #[cfg(any(has_fpu, test))] pub fpccr: RW<u32>, /// Floating Point Context Address - #[cfg(any(has_fpu, test))] pub fpcar: RW<u32>, /// Floating Point Default Status Control - #[cfg(any(has_fpu, test))] pub fpdscr: RW<u32>, /// Media and FP Feature - #[cfg(any(has_fpu, test))] pub mvfr: [RO<u32>; 3], } diff --git a/src/peripheral/itm.rs b/src/peripheral/itm.rs index fd4a2fd..b424817 100644 --- a/src/peripheral/itm.rs +++ b/src/peripheral/itm.rs @@ -1,4 +1,6 @@ //! Instrumentation Trace Macrocell +//! +//! *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`) use core::cell::UnsafeCell; use core::ptr; diff --git a/src/peripheral/mod.rs b/src/peripheral/mod.rs index ffbb56c..2abe79f 100644 --- a/src/peripheral/mod.rs +++ b/src/peripheral/mod.rs @@ -70,22 +70,27 @@ #![allow(private_no_mangle_statics)] use core::marker::PhantomData; -use core::ops::{Deref, DerefMut}; +use core::ops; use interrupt; -#[cfg(armv7m)] +#[cfg(any(armv7m, target_arch = "x86_64"))] pub mod cbp; pub mod cpuid; pub mod dcb; pub mod dwt; +#[cfg(any(armv7m, target_arch = "x86_64"))] pub mod fpb; +#[cfg(any(has_fpu, target_arch = "x86_64"))] pub mod fpu; +// NOTE(target_arch) is for documentation purposes +#[cfg(any(armv7m, target_arch = "x86_64"))] pub mod itm; pub mod mpu; pub mod nvic; pub mod scb; pub mod syst; +#[cfg(any(armv7m, target_arch = "x86_64"))] pub mod tpiu; #[cfg(test)] @@ -97,7 +102,7 @@ mod test; #[allow(non_snake_case)] pub struct Peripherals { /// Cache and branch predictor maintenance operations - #[cfg(armv7m)] + #[cfg(any(armv7m, target_arch = "x86_64"))] pub CBP: CBP, /// CPUID pub CPUID: CPUID, @@ -106,10 +111,13 @@ pub struct Peripherals { /// Data Watchpoint and Trace unit pub DWT: DWT, /// Flash Patch and Breakpoint unit + #[cfg(any(armv7m, target_arch = "x86_64"))] pub FPB: FPB, /// Floating Point Unit + #[cfg(any(has_fpu, target_arch = "x86_64"))] pub FPU: FPU, /// Instrumentation Trace Macrocell + #[cfg(any(armv7m, target_arch = "x86_64"))] pub ITM: ITM, /// Memory Protection Unit pub MPU: MPU, @@ -120,6 +128,7 @@ pub struct Peripherals { /// SysTick: System Timer pub SYST: SYST, /// Trace Port Interface Unit; + #[cfg(any(armv7m, target_arch = "x86_64"))] pub TPIU: TPIU, } @@ -148,7 +157,7 @@ impl Peripherals { CORE_PERIPHERALS = true; Peripherals { - #[cfg(armv7m)] + #[cfg(any(armv7m, target_arch = "x86_64"))] CBP: CBP { _marker: PhantomData, }, @@ -161,12 +170,15 @@ impl Peripherals { DWT: DWT { _marker: PhantomData, }, + #[cfg(any(armv7m, target_arch = "x86_64"))] FPB: FPB { _marker: PhantomData, }, + #[cfg(any(has_fpu, target_arch = "x86_64"))] FPU: FPU { _marker: PhantomData, }, + #[cfg(any(armv7m, target_arch = "x86_64"))] ITM: ITM { _marker: PhantomData, }, @@ -182,6 +194,7 @@ impl Peripherals { SYST: SYST { _marker: PhantomData, }, + #[cfg(any(armv7m, target_arch = "x86_64"))] TPIU: TPIU { _marker: PhantomData, }, @@ -190,12 +203,14 @@ impl Peripherals { } /// Cache and branch predictor maintenance operations -#[cfg(armv7m)] +/// +/// *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`) +#[cfg(any(armv7m, target_arch = "x86_64"))] pub struct CBP { _marker: PhantomData<*const ()>, } -#[cfg(armv7m)] +#[cfg(any(armv7m, target_arch = "x86_64"))] impl CBP { pub(crate) unsafe fn new() -> Self { CBP { @@ -209,11 +224,11 @@ impl CBP { } } -#[cfg(armv7m)] +#[cfg(any(armv7m, target_arch = "x86_64"))] unsafe impl Send for CBP {} -#[cfg(armv7m)] -impl Deref for CBP { +#[cfg(any(armv7m, target_arch = "x86_64"))] +impl ops::Deref for CBP { type Target = self::cbp::RegisterBlock; fn deref(&self) -> &Self::Target { @@ -233,7 +248,7 @@ impl CPUID { } } -impl Deref for CPUID { +impl ops::Deref for CPUID { type Target = self::cpuid::RegisterBlock; fn deref(&self) -> &Self::Target { @@ -253,7 +268,7 @@ impl DCB { } } -impl Deref for DCB { +impl ops::Deref for DCB { type Target = self::dcb::RegisterBlock; fn deref(&self) -> &Self::Target { @@ -273,7 +288,7 @@ impl DWT { } } -impl Deref for DWT { +impl ops::Deref for DWT { type Target = self::dwt::RegisterBlock; fn deref(&self) -> &Self::Target { @@ -282,10 +297,14 @@ impl Deref for DWT { } /// Flash Patch and Breakpoint unit +/// +/// *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`) +#[cfg(any(armv7m, target_arch = "x86_64"))] pub struct FPB { _marker: PhantomData<*const ()>, } +#[cfg(any(armv7m, target_arch = "x86_64"))] impl FPB { /// Returns a pointer to the register block pub fn ptr() -> *const fpb::RegisterBlock { @@ -293,7 +312,8 @@ impl FPB { } } -impl Deref for FPB { +#[cfg(any(armv7m, target_arch = "x86_64"))] +impl ops::Deref for FPB { type Target = self::fpb::RegisterBlock; fn deref(&self) -> &Self::Target { @@ -302,10 +322,14 @@ impl Deref for FPB { } /// Floating Point Unit +/// +/// *NOTE* Available only on ARMv7E-M (`thumbv7em-none-eabihf`) +#[cfg(any(has_fpu, target_arch = "x86_64"))] pub struct FPU { _marker: PhantomData<*const ()>, } +#[cfg(any(has_fpu, target_arch = "x86_64"))] impl FPU { /// Returns a pointer to the register block pub fn ptr() -> *const fpu::RegisterBlock { @@ -313,8 +337,8 @@ impl FPU { } } -#[cfg(any(has_fpu, test))] -impl Deref for FPU { +#[cfg(any(has_fpu, target_arch = "x86_64"))] +impl ops::Deref for FPU { type Target = self::fpu::RegisterBlock; fn deref(&self) -> &Self::Target { @@ -323,10 +347,14 @@ impl Deref for FPU { } /// Instrumentation Trace Macrocell +/// +/// *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`) +#[cfg(any(armv7m, target_arch = "x86_64"))] pub struct ITM { _marker: PhantomData<*const ()>, } +#[cfg(any(armv7m, target_arch = "x86_64"))] impl ITM { /// Returns a pointer to the register block pub fn ptr() -> *mut itm::RegisterBlock { @@ -334,7 +362,8 @@ impl ITM { } } -impl Deref for ITM { +#[cfg(any(armv7m, target_arch = "x86_64"))] +impl ops::Deref for ITM { type Target = self::itm::RegisterBlock; fn deref(&self) -> &Self::Target { @@ -342,7 +371,8 @@ impl Deref for ITM { } } -impl DerefMut for ITM { +#[cfg(any(armv7m, target_arch = "x86_64"))] +impl ops::DerefMut for ITM { fn deref_mut(&mut self) -> &mut Self::Target { unsafe { &mut *Self::ptr() } } @@ -360,7 +390,7 @@ impl MPU { } } -impl Deref for MPU { +impl ops::Deref for MPU { type Target = self::mpu::RegisterBlock; fn deref(&self) -> &Self::Target { @@ -380,7 +410,7 @@ impl NVIC { } } -impl Deref for NVIC { +impl ops::Deref for NVIC { type Target = self::nvic::RegisterBlock; fn deref(&self) -> &Self::Target { @@ -400,7 +430,7 @@ impl SCB { } } -impl Deref for SCB { +impl ops::Deref for SCB { type Target = self::scb::RegisterBlock; fn deref(&self) -> &Self::Target { @@ -420,7 +450,7 @@ impl SYST { } } -impl Deref for SYST { +impl ops::Deref for SYST { type Target = self::syst::RegisterBlock; fn deref(&self) -> &Self::Target { @@ -429,10 +459,14 @@ impl Deref for SYST { } /// Trace Port Interface Unit; +/// +/// *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`) +#[cfg(any(armv7m, target_arch = "x86_64"))] pub struct TPIU { _marker: PhantomData<*const ()>, } +#[cfg(any(armv7m, target_arch = "x86_64"))] impl TPIU { /// Returns a pointer to the register block pub fn ptr() -> *const tpiu::RegisterBlock { @@ -440,7 +474,8 @@ impl TPIU { } } -impl Deref for TPIU { +#[cfg(any(armv7m, target_arch = "x86_64"))] +impl ops::Deref for TPIU { type Target = self::tpiu::RegisterBlock; fn deref(&self) -> &Self::Target { diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs index 9a922c7..41f3825 100644 --- a/src/peripheral/scb.rs +++ b/src/peripheral/scb.rs @@ -2,11 +2,11 @@ use volatile_register::RW; -#[cfg(any(armv7m, has_fpu))] +#[cfg(any(armv7m, has_fpu, target_arch = "x86_64"))] use super::{CBP, SCB}; -#[cfg(armv7m)] +#[cfg(any(armv7m, target_arch = "x86_64"))] use super::CPUID; -#[cfg(armv7m)] +#[cfg(any(armv7m, target_arch = "x86_64"))] use super::cpuid::CsselrCacheType; /// Register block @@ -108,16 +108,16 @@ impl SCB { } } -#[cfg(armv7m)] +#[cfg(any(armv7m, target_arch = "x86_64"))] mod scb_consts { pub const SCB_CCR_IC_MASK: u32 = (1 << 17); pub const SCB_CCR_DC_MASK: u32 = (1 << 16); } -#[cfg(armv7m)] +#[cfg(any(armv7m, target_arch = "x86_64"))] use self::scb_consts::*; -#[cfg(armv7m)] +#[cfg(any(armv7m, target_arch = "x86_64"))] impl SCB { /// Enables I-Cache if currently disabled #[inline] diff --git a/src/peripheral/tpiu.rs b/src/peripheral/tpiu.rs index 7a08805..4115bb3 100644 --- a/src/peripheral/tpiu.rs +++ b/src/peripheral/tpiu.rs @@ -1,4 +1,6 @@ //! Trace Port Interface Unit; +//! +//! *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`) use volatile_register::{RO, RW, WO}; |