diff options
| -rw-r--r-- | CHANGELOG.md | 7 | ||||
| -rw-r--r-- | src/peripheral/mod.rs | 2 | ||||
| -rw-r--r-- | src/register/basepri.rs | 2 |
3 files changed, 9 insertions, 2 deletions
diff --git a/CHANGELOG.md b/CHANGELOG.md index 90a89d1..9e25aab 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -7,6 +7,13 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] +### Fixed + +- MEMORY SAFETY. Some concurrency models that use "partial" critical sections + (cf. BASEPRI) can be broken by changing the priority of interrupts or by + changing BASEPRI in some scenarios. For this reason `NVIC.set_priority` and + `register::basepri::write` are now `unsafe`. + ## [v0.2.2] - 2017-04-08 ### Fixed diff --git a/src/peripheral/mod.rs b/src/peripheral/mod.rs index 1f9e147..d14d782 100644 --- a/src/peripheral/mod.rs +++ b/src/peripheral/mod.rs @@ -380,7 +380,7 @@ impl Nvic { /// /// NOTE See `get_priority` method for an explanation of how NVIC priorities /// work. - pub fn set_priority<I>(&self, interrupt: I, prio: u8) + pub unsafe fn set_priority<I>(&self, interrupt: I, prio: u8) where I: Nr, { diff --git a/src/register/basepri.rs b/src/register/basepri.rs index e9164c1..d5ec002 100644 --- a/src/register/basepri.rs +++ b/src/register/basepri.rs @@ -16,7 +16,7 @@ pub fn read() -> u8 { /// Writes to the CPU register #[inline(always)] -pub fn write(basepri: u8) { +pub unsafe fn write(basepri: u8) { unsafe { asm!("msr BASEPRI, $0" : |