1 files changed, 23 insertions, 21 deletions

diff --git a/src/peripheral/cbp.rs b/src/peripheral/cbp.rs
index 3397fff..590cb7b 100644
--- a/src/peripheral/cbp.rs
+++ b/src/peripheral/cbp.rs
@@ -2,6 +2,8 @@
 
 use volatile_register::WO;
 
+use peripheral::CBP;
+
 /// Register block
 #[repr(C)]
 pub struct RegisterBlock {
@@ -33,26 +35,26 @@ const CBP_SW_WAY_MASK: u32 = 0x3 << CBP_SW_WAY_POS;
 const CBP_SW_SET_POS: u32 = 5;
 const CBP_SW_SET_MASK: u32 = 0x1FF << CBP_SW_SET_POS;
 
-impl RegisterBlock {
+impl CBP {
     /// I-cache invalidate all to PoU
-    #[inline(always)]
-    pub fn iciallu(&self) {
+    #[inline]
+    pub fn iciallu(&mut self) {
         unsafe {
             self.iciallu.write(0);
         }
     }
 
     /// I-cache invalidate by MVA to PoU
-    #[inline(always)]
-    pub fn icimvau(&self, mva: u32) {
+    #[inline]
+    pub fn icimvau(&mut self, mva: u32) {
         unsafe {
             self.icimvau.write(mva);
         }
     }
 
     /// D-cache invalidate by MVA to PoC
-    #[inline(always)]
-    pub fn dcimvac(&self, mva: u32) {
+    #[inline]
+    pub fn dcimvac(&mut self, mva: u32) {
         unsafe {
             self.dcimvac.write(mva);
         }
@@ -61,8 +63,8 @@ impl RegisterBlock {
     /// D-cache invalidate by set-way
     ///
     /// `set` is masked to be between 0 and 3, and `way` between 0 and 511.
-    #[inline(always)]
-    pub fn dcisw(&self, set: u16, way: u16) {
+    #[inline]
+    pub fn dcisw(&mut self, set: u16, way: u16) {
         // The ARMv7-M Architecture Reference Manual, as of Revision E.b, says these set/way
         // operations have a register data format which depends on the implementation's
         // associativity and number of sets. Specifically the 'way' and 'set' fields have
@@ -81,16 +83,16 @@ impl RegisterBlock {
     }
 
     /// D-cache clean by MVA to PoU
-    #[inline(always)]
-    pub fn dccmvau(&self, mva: u32) {
+    #[inline]
+    pub fn dccmvau(&mut self, mva: u32) {
         unsafe {
             self.dccmvau.write(mva);
         }
     }
 
     /// D-cache clean by MVA to PoC
-    #[inline(always)]
-    pub fn dccmvac(&self, mva: u32) {
+    #[inline]
+    pub fn dccmvac(&mut self, mva: u32) {
         unsafe {
             self.dccmvac.write(mva);
         }
@@ -99,8 +101,8 @@ impl RegisterBlock {
     /// D-cache clean by set-way
     ///
     /// `set` is masked to be between 0 and 3, and `way` between 0 and 511.
-    #[inline(always)]
-    pub fn dccsw(&self, set: u16, way: u16) {
+    #[inline]
+    pub fn dccsw(&mut self, set: u16, way: u16) {
         // See comment for dcisw() about the format here
         unsafe {
             self.dccsw.write(
@@ -111,8 +113,8 @@ impl RegisterBlock {
     }
 
     /// D-cache clean and invalidate by MVA to PoC
-    #[inline(always)]
-    pub fn dccimvac(&self, mva: u32) {
+    #[inline]
+    pub fn dccimvac(&mut self, mva: u32) {
         unsafe {
             self.dccimvac.write(mva);
         }
@@ -121,8 +123,8 @@ impl RegisterBlock {
     /// D-cache clean and invalidate by set-way
     ///
     /// `set` is masked to be between 0 and 3, and `way` between 0 and 511.
-    #[inline(always)]
-    pub fn dccisw(&self, set: u16, way: u16) {
+    #[inline]
+    pub fn dccisw(&mut self, set: u16, way: u16) {
         // See comment for dcisw() about the format here
         unsafe {
             self.dccisw.write(
@@ -133,8 +135,8 @@ impl RegisterBlock {
     }
 
     /// Branch predictor invalidate all
-    #[inline(always)]
-    pub fn bpiall(&self) {
+    #[inline]
+    pub fn bpiall(&mut self) {
         unsafe {
             self.bpiall.write(0);
         }