diff options
Diffstat (limited to 'src/peripheral/scb.rs')
| -rw-r--r-- | src/peripheral/scb.rs | 211 |
1 files changed, 206 insertions, 5 deletions
diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs index ba36093..c82e098 100644 --- a/src/peripheral/scb.rs +++ b/src/peripheral/scb.rs @@ -7,9 +7,9 @@ use volatile_register::RW; #[cfg(not(armv6m))] use super::cpuid::CsselrCacheType; #[cfg(not(armv6m))] -use super::CPUID; -#[cfg(not(armv6m))] use super::CBP; +#[cfg(not(armv6m))] +use super::CPUID; use super::SCB; /// Register block @@ -19,10 +19,7 @@ pub struct RegisterBlock { pub icsr: RW<u32>, /// Vector Table Offset (not present on Cortex-M0 variants) - #[cfg(not(armv6m))] pub vtor: RW<u32>, - #[cfg(armv6m)] - _reserved0: u32, /// Application Interrupt and Reset Control pub aircr: RW<u32>, @@ -598,3 +595,207 @@ impl SCB { } } } + +const SCB_SCR_SLEEPONEXIT: u32 = 0x1 << 1; + +impl SCB { + /// Set the SLEEPONEXIT bit in the SCR register + pub fn set_sleeponexit(&mut self) { + unsafe { + self.scr.modify(|scr| scr | SCB_SCR_SLEEPONEXIT); + } + } + + /// Clear the SLEEPONEXIT bit in the SCR register + pub fn clear_sleeponexit(&mut self) { + unsafe { + self.scr.modify(|scr| scr & !SCB_SCR_SLEEPONEXIT); + } + } +} + +const SCB_AIRCR_VECTKEY: u32 = 0x05FA << 16; +const SCB_AIRCR_PRIGROUP_MASK: u32 = 0x5 << 8; +const SCB_AIRCR_SYSRESETREQ: u32 = 1 << 2; + +impl SCB { + /// Initiate a system reset request to reset the MCU + pub fn system_reset(&mut self) -> ! { + ::asm::dsb(); + unsafe { + self.aircr.modify( + |r| { + SCB_AIRCR_VECTKEY | // otherwise the write is ignored + r & SCB_AIRCR_PRIGROUP_MASK | // keep priority group unchanged + SCB_AIRCR_SYSRESETREQ + }, // set the bit + ) + }; + ::asm::dsb(); + loop { + // wait for the reset + ::asm::nop(); // avoid rust-lang/rust#28728 + } + } +} + +const SCB_ICSR_PENDSVSET: u32 = 1 << 28; +const SCB_ICSR_PENDSVCLR: u32 = 1 << 27; + +const SCB_ICSR_PENDSTSET: u32 = 1 << 26; +const SCB_ICSR_PENDSTCLR: u32 = 1 << 25; + +impl SCB { + /// Set the PENDSVSET bit in the ICSR register which will pend the PendSV interrupt + pub fn set_pendsv() { + unsafe { + (*Self::ptr()).icsr.write(SCB_ICSR_PENDSVSET); + } + } + + /// Check if PENDSVSET bit in the ICSR register is set meaning PendSV interrupt is pending + pub fn is_pendsv_pending() -> bool { + unsafe { (*Self::ptr()).icsr.read() & SCB_ICSR_PENDSVSET == SCB_ICSR_PENDSVSET } + } + + /// Set the PENDSVCLR bit in the ICSR register which will clear a pending PendSV interrupt + pub fn clear_pendsv() { + unsafe { + (*Self::ptr()).icsr.write(SCB_ICSR_PENDSVCLR); + } + } + + /// Set the PENDSTCLR bit in the ICSR register which will clear a pending SysTick interrupt + #[inline] + pub fn set_pendst() { + unsafe { + (*Self::ptr()).icsr.write(SCB_ICSR_PENDSTSET); + } + } + + /// Check if PENDSTSET bit in the ICSR register is set meaning SysTick interrupt is pending + #[inline] + pub fn is_pendst_pending() -> bool { + unsafe { (*Self::ptr()).icsr.read() & SCB_ICSR_PENDSTSET == SCB_ICSR_PENDSTSET } + } + + /// Set the PENDSTCLR bit in the ICSR register which will clear a pending SysTick interrupt + #[inline] + pub fn clear_pendst() { + unsafe { + (*Self::ptr()).icsr.write(SCB_ICSR_PENDSTCLR); + } + } +} + +/// System handlers, exceptions with configurable priority +#[allow(non_camel_case_types)] +#[derive(Clone, Copy, Debug, Eq, PartialEq)] +pub enum SystemHandler { + // NonMaskableInt, // priority is fixed + // HardFault, // priority is fixed + /// Memory management interrupt (not present on Cortex-M0 variants) + #[cfg(not(armv6m))] + MemoryManagement, + + /// Bus fault interrupt (not present on Cortex-M0 variants) + #[cfg(not(armv6m))] + BusFault, + + /// Usage fault interrupt (not present on Cortex-M0 variants) + #[cfg(not(armv6m))] + UsageFault, + + /// Secure fault interrupt (only on ARMv8-M) + #[cfg(any(armv8m, target_arch = "x86_64"))] + SecureFault, + + /// SV call interrupt + SVCall, + + /// Debug monitor interrupt (not present on Cortex-M0 variants) + #[cfg(not(armv6m))] + DebugMonitor, + + /// Pend SV interrupt + PendSV, + + /// System Tick interrupt + SysTick, +} + +impl SystemHandler { + fn index(&self) -> u8 { + match *self { + #[cfg(not(armv6m))] + SystemHandler::MemoryManagement => 4, + #[cfg(not(armv6m))] + SystemHandler::BusFault => 5, + #[cfg(not(armv6m))] + SystemHandler::UsageFault => 6, + #[cfg(any(armv8m, target_arch = "x86_64"))] + SystemHandler::SecureFault => 7, + SystemHandler::SVCall => 11, + #[cfg(not(armv6m))] + SystemHandler::DebugMonitor => 12, + SystemHandler::PendSV => 14, + SystemHandler::SysTick => 15, + } + } +} + +impl SCB { + /// Returns the hardware priority of `system_handler` + /// + /// *NOTE*: Hardware priority does not exactly match logical priority levels. See + /// [`NVIC.get_priority`](struct.NVIC.html#method.get_priority) for more details. + pub fn get_priority(system_handler: SystemHandler) -> u8 { + let index = system_handler.index(); + + #[cfg(not(armv6m))] + { + // NOTE(unsafe) atomic read with no side effects + unsafe { (*Self::ptr()).shpr[usize::from(index - 4)].read() } + } + + #[cfg(armv6m)] + { + // NOTE(unsafe) atomic read with no side effects + let shpr = unsafe { (*Self::ptr()).shpr[usize::from((index - 8) / 4)].read() }; + let prio = (shpr >> (8 * (index % 4))) & 0x000000ff; + prio as u8 + } + } + + /// Sets the hardware priority of `system_handler` to `prio` + /// + /// *NOTE*: Hardware priority does not exactly match logical priority levels. See + /// [`NVIC.get_priority`](struct.NVIC.html#method.get_priority) for more details. + /// + /// On ARMv6-M, updating a system handler priority requires a read-modify-write operation. On + /// ARMv7-M, the operation is performed in a single, atomic write operation. + /// + /// # Unsafety + /// + /// Changing priority levels can break priority-based critical sections (see + /// [`register::basepri`](../register/basepri/index.html)) and compromise memory safety. + pub unsafe fn set_priority(&mut self, system_handler: SystemHandler, prio: u8) { + let index = system_handler.index(); + + #[cfg(not(armv6m))] + { + self.shpr[usize::from(index - 4)].write(prio) + } + + #[cfg(armv6m)] + { + self.shpr[usize::from((index - 8) / 4)].modify(|value| { + let shift = 8 * (index % 4); + let mask = 0x000000ff << shift; + let prio = u32::from(prio) << shift; + + (value & !mask) | prio + }); + } + } +} |