diff options
Diffstat (limited to 'src/peripheral/scb.rs')
| -rw-r--r-- | src/peripheral/scb.rs | 26 |
1 files changed, 17 insertions, 9 deletions
diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs index 7fb4505..001bb14 100644 --- a/src/peripheral/scb.rs +++ b/src/peripheral/scb.rs @@ -331,11 +331,15 @@ impl SCB { cbp.iciallu(); // Enable I-cache - // NOTE(unsafe): We have synchronised access by &mut self - unsafe { self.ccr.modify(|r| r | SCB_CCR_IC_MASK) }; + extern "C" { + // see asm-v7m.s + fn __enable_icache(); + } - crate::asm::dsb(); - crate::asm::isb(); + // NOTE(unsafe): The asm routine manages exclusive access to the SCB + // registers and applies the proper barriers; it is technically safe on + // its own, and is only `unsafe` here because it's `extern "C"`. + unsafe { __enable_icache(); } } /// Disables I-cache if currently enabled. @@ -400,11 +404,15 @@ impl SCB { unsafe { self.invalidate_dcache(cpuid) }; // Now turn on the D-cache - // NOTE(unsafe): We have synchronised access by &mut self - unsafe { self.ccr.modify(|r| r | SCB_CCR_DC_MASK) }; + extern "C" { + // see asm-v7m.s + fn __enable_dcache(); + } - crate::asm::dsb(); - crate::asm::isb(); + // NOTE(unsafe): The asm routine manages exclusive access to the SCB + // registers and applies the proper barriers; it is technically safe on + // its own, and is only `unsafe` here because it's `extern "C"`. + unsafe { __enable_dcache(); } } /// Disables D-cache if currently enabled. @@ -877,7 +885,7 @@ impl SCB { } } - /// Set the PENDSTCLR bit in the ICSR register which will clear a pending SysTick interrupt + /// Set the PENDSTSET bit in the ICSR register which will pend a SysTick interrupt #[inline] pub fn set_pendst() { unsafe { |