diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/itm.rs | 12 | ||||
| -rw-r--r-- | src/peripheral/itm.rs | 6 | ||||
| -rw-r--r-- | src/peripheral/mod.rs | 12 | ||||
| -rw-r--r-- | src/register/basepri.rs | 15 | ||||
| -rw-r--r-- | src/register/basepri_max.rs | 15 |
5 files changed, 44 insertions, 16 deletions
@@ -7,7 +7,7 @@ use aligned::Aligned; use peripheral::itm::Stim; // NOTE assumes that `bytes` is 32-bit aligned -unsafe fn write_words(stim: &Stim, bytes: &[u32]) { +unsafe fn write_words(stim: &mut Stim, bytes: &[u32]) { let mut p = bytes.as_ptr(); for _ in 0..bytes.len() { while !stim.is_fifo_ready() {} @@ -16,7 +16,7 @@ unsafe fn write_words(stim: &Stim, bytes: &[u32]) { } } -struct Port<'p>(&'p Stim); +struct Port<'p>(&'p mut Stim); impl<'p> fmt::Write for Port<'p> { fn write_str(&mut self, s: &str) -> fmt::Result { @@ -26,7 +26,7 @@ impl<'p> fmt::Write for Port<'p> { } /// Writes a `buffer` to the ITM `port` -pub fn write_all(port: &Stim, buffer: &[u8]) { +pub fn write_all(port: &mut Stim, buffer: &[u8]) { unsafe { let mut len = buffer.len(); let mut ptr = buffer.as_ptr(); @@ -84,7 +84,7 @@ pub fn write_all(port: &Stim, buffer: &[u8]) { /// // Or equivalently /// itm::write_aligned(&itm.stim[0], &Aligned(*b"Hello, world!\n")); /// ``` -pub fn write_aligned(port: &Stim, buffer: &Aligned<u32, [u8]>) { +pub fn write_aligned(port: &mut Stim, buffer: &Aligned<u32, [u8]>) { unsafe { let len = buffer.len(); @@ -120,13 +120,13 @@ pub fn write_aligned(port: &Stim, buffer: &Aligned<u32, [u8]>) { } /// Writes `fmt::Arguments` to the ITM `port` -pub fn write_fmt(port: &Stim, args: fmt::Arguments) { +pub fn write_fmt(port: &mut Stim, args: fmt::Arguments) { use core::fmt::Write; Port(port).write_fmt(args).ok(); } /// Writes a string to the ITM `port` -pub fn write_str(port: &Stim, string: &str) { +pub fn write_str(port: &mut Stim, string: &str) { write_all(port, string.as_bytes()) } diff --git a/src/peripheral/itm.rs b/src/peripheral/itm.rs index 17cf869..fd4a2fd 100644 --- a/src/peripheral/itm.rs +++ b/src/peripheral/itm.rs @@ -33,17 +33,17 @@ pub struct Stim { impl Stim { /// Writes an `u8` payload into the stimulus port - pub fn write_u8(&self, value: u8) { + pub fn write_u8(&mut self, value: u8) { unsafe { ptr::write_volatile(self.register.get() as *mut u8, value) } } /// Writes an `u16` payload into the stimulus port - pub fn write_u16(&self, value: u16) { + pub fn write_u16(&mut self, value: u16) { unsafe { ptr::write_volatile(self.register.get() as *mut u16, value) } } /// Writes an `u32` payload into the stimulus port - pub fn write_u32(&self, value: u32) { + pub fn write_u32(&mut self, value: u32) { unsafe { ptr::write_volatile(self.register.get(), value) } } diff --git a/src/peripheral/mod.rs b/src/peripheral/mod.rs index adeeacb..ffbb56c 100644 --- a/src/peripheral/mod.rs +++ b/src/peripheral/mod.rs @@ -70,7 +70,7 @@ #![allow(private_no_mangle_statics)] use core::marker::PhantomData; -use core::ops::Deref; +use core::ops::{Deref, DerefMut}; use interrupt; @@ -329,8 +329,8 @@ pub struct ITM { impl ITM { /// Returns a pointer to the register block - pub fn ptr() -> *const itm::RegisterBlock { - 0xE000_0000 as *const _ + pub fn ptr() -> *mut itm::RegisterBlock { + 0xE000_0000 as *mut _ } } @@ -342,6 +342,12 @@ impl Deref for ITM { } } +impl DerefMut for ITM { + fn deref_mut(&mut self) -> &mut Self::Target { + unsafe { &mut *Self::ptr() } + } +} + /// Memory Protection Unit pub struct MPU { _marker: PhantomData<*const ()>, diff --git a/src/register/basepri.rs b/src/register/basepri.rs index a024d74..c9be9d3 100644 --- a/src/register/basepri.rs +++ b/src/register/basepri.rs @@ -18,11 +18,22 @@ pub fn read() -> u8 { } /// Writes to the CPU register +/// +/// **IMPORTANT** If you are using a Cortex-M7 device with revision r0p1 you MUST enable the +/// `cm7-r0p1` Cargo feature or this function WILL misbehave. +#[cfg_attr(not(target_arch = "arm"), allow(unused_variables))] #[inline] -pub unsafe fn write(_basepri: u8) { +pub unsafe fn write(basepri: u8) { match () { #[cfg(target_arch = "arm")] - () => asm!("msr BASEPRI, $0" :: "r"(_basepri) : "memory" : "volatile"), + () => match () { + #[cfg(not(feature = "cm7-r0p1"))] + () => asm!("msr BASEPRI, $0" :: "r"(basepri) : "memory" : "volatile"), + #[cfg(feature = "cm7-r0p1")] + () => asm!("cpsid i + msr BASEPRI, $0 + cpsie i" :: "r"(basepri) : "memory" : "volatile"), + }, #[cfg(not(target_arch = "arm"))] () => unimplemented!(), } diff --git a/src/register/basepri_max.rs b/src/register/basepri_max.rs index 0833aa7..c386e86 100644 --- a/src/register/basepri_max.rs +++ b/src/register/basepri_max.rs @@ -4,12 +4,23 @@ /// /// - `basepri != 0` AND `basepri::read() == 0`, OR /// - `basepri != 0` AND `basepri < basepri::read()` +/// +/// **IMPORTANT** If you are using a Cortex-M7 device with revision r0p1 you MUST enable the +/// `cm7-r0p1` Cargo feature or this function WILL misbehave. +#[cfg_attr(not(target_arch = "arm"), allow(unused_variables))] #[inline] -pub fn write(_basepri: u8) { +pub fn write(basepri: u8) { match () { #[cfg(target_arch = "arm")] () => unsafe { - asm!("msr BASEPRI_MAX, $0" :: "r"(_basepri) : "memory" : "volatile"); + match () { + #[cfg(not(feature = "cm7-r0p1"))] + () => asm!("msr BASEPRI_MAX, $0" :: "r"(basepri) : "memory" : "volatile"), + #[cfg(feature = "cm7-r0p1")] + () => asm!("cpsid i + msr BASEPRI_MAX, $0 + cpsie i" :: "r"(basepri) : "memory" : "volatile"), + } }, #[cfg(not(target_arch = "arm"))] () => unimplemented!(), |