diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/macros.rs | 6 | ||||
| -rw-r--r-- | src/peripheral/dcb.rs | 21 |
2 files changed, 24 insertions, 3 deletions
diff --git a/src/macros.rs b/src/macros.rs index e41cdc5..813552f 100644 --- a/src/macros.rs +++ b/src/macros.rs @@ -13,13 +13,13 @@ macro_rules! iprint { #[macro_export] macro_rules! iprintln { ($channel:expr) => { - iprint!($channel, "\n"); + $crate::itm::write_str($channel, "\n"); }; ($channel:expr, $fmt:expr) => { - iprint!($channel, concat!($fmt, "\n")); + $crate::itm::write_str($channel, concat!($fmt, "\n")); }; ($channel:expr, $fmt:expr, $($arg:tt)*) => { - iprint!($channel, concat!($fmt, "\n"), $($arg)*); + $crate::itm::write_fmt($channel, format_args!(concat!($fmt, "\n"), $($arg)*)); }; } diff --git a/src/peripheral/dcb.rs b/src/peripheral/dcb.rs index 02ec901..14dc75b 100644 --- a/src/peripheral/dcb.rs +++ b/src/peripheral/dcb.rs @@ -2,6 +2,10 @@ use volatile_register::{RW, WO}; +use peripheral::DCB; + +const DCB_DEMCR_TRCENA: u32 = 1 << 24; + /// Register block #[repr(C)] pub struct RegisterBlock { @@ -14,3 +18,20 @@ pub struct RegisterBlock { /// Debug Exception and Monitor Control pub demcr: RW<u32>, } + +impl DCB { + /// Enables TRACE. This is for example required by the + /// `peripheral::DWT` cycle counter to work properly. + /// As by STM documentation, this flag is not reset on + /// soft-reset, only on power reset. + pub fn enable_trace(&mut self) { + // set bit 24 / TRCENA + unsafe { self.demcr.modify(|w| w | DCB_DEMCR_TRCENA); } + } + + /// Disables TRACE. See `DCB::enable_trace()` for more details + pub fn disable_trace(&mut self) { + // unset bit 24 / TRCENA + unsafe { self.demcr.modify(|w| w & !DCB_DEMCR_TRCENA); } + } +} |