diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/delay.rs | 5 | ||||
| -rw-r--r-- | src/interrupt.rs | 5 | ||||
| -rw-r--r-- | src/itm.rs | 4 | ||||
| -rw-r--r-- | src/peripheral/dcb.rs | 2 | ||||
| -rw-r--r-- | src/peripheral/scb.rs | 20 |
5 files changed, 25 insertions, 11 deletions
diff --git a/src/delay.rs b/src/delay.rs index 051151f..2f5b8e0 100644 --- a/src/delay.rs +++ b/src/delay.rs @@ -17,7 +17,10 @@ impl Delay { pub fn new(mut syst: SYST, ahb_frequency: u32) -> Self { syst.set_clock_source(SystClkSource::Core); - Delay { syst, ahb_frequency } + Delay { + syst, + ahb_frequency, + } } /// Releases the system timer (SysTick) resource. diff --git a/src/interrupt.rs b/src/interrupt.rs index ad76ff2..b5fcab6 100644 --- a/src/interrupt.rs +++ b/src/interrupt.rs @@ -25,7 +25,10 @@ pub unsafe trait InterruptNumber: Copy { /// Implement InterruptNumber for the old bare_metal::Nr trait. /// This implementation is for backwards compatibility only and will be removed in cortex-m 0.8. -#[deprecated(since="0.7.0", note="Please update your PAC to one using the latest svd2rust")] +#[deprecated( + since = "0.7.0", + note = "Please update your PAC to one using the latest svd2rust" +)] unsafe impl<T: Nr + Copy> InterruptNumber for T { fn number(self) -> u16 { self.nr() as u16 @@ -140,9 +140,7 @@ pub fn write_all(port: &mut Stim, buffer: &[u8]) { /// ``` #[allow(clippy::missing_inline_in_public_items)] pub fn write_aligned(port: &mut Stim, buffer: &Aligned<[u8]>) { - unsafe { - write_aligned_impl(port, &buffer.0) - } + unsafe { write_aligned_impl(port, &buffer.0) } } /// Writes `fmt::Arguments` to the ITM `port` diff --git a/src/peripheral/dcb.rs b/src/peripheral/dcb.rs index 45bd5d2..5689cb4 100644 --- a/src/peripheral/dcb.rs +++ b/src/peripheral/dcb.rs @@ -2,8 +2,8 @@ use volatile_register::{RW, WO}; -use core::ptr; use crate::peripheral::DCB; +use core::ptr; const DCB_DEMCR_TRCENA: u32 = 1 << 24; diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs index 001bb14..1b25b5f 100644 --- a/src/peripheral/scb.rs +++ b/src/peripheral/scb.rs @@ -339,7 +339,9 @@ impl SCB { // NOTE(unsafe): The asm routine manages exclusive access to the SCB // registers and applies the proper barriers; it is technically safe on // its own, and is only `unsafe` here because it's `extern "C"`. - unsafe { __enable_icache(); } + unsafe { + __enable_icache(); + } } /// Disables I-cache if currently enabled. @@ -412,7 +414,9 @@ impl SCB { // NOTE(unsafe): The asm routine manages exclusive access to the SCB // registers and applies the proper barriers; it is technically safe on // its own, and is only `unsafe` here because it's `extern "C"`. - unsafe { __enable_dcache(); } + unsafe { + __enable_dcache(); + } } /// Disables D-cache if currently enabled. @@ -960,7 +964,7 @@ impl SCB { // NOTE(unsafe): Index is bounded to [4,15] by SystemHandler design. // TODO: Review it after rust-lang/rust/issues/13926 will be fixed. - let priority_ref = unsafe {(*Self::ptr()).shpr.get_unchecked(usize::from(index - 4))}; + let priority_ref = unsafe { (*Self::ptr()).shpr.get_unchecked(usize::from(index - 4)) }; priority_ref.read() } @@ -971,7 +975,11 @@ impl SCB { // NOTE(unsafe): Index is bounded to [11,15] by SystemHandler design. // TODO: Review it after rust-lang/rust/issues/13926 will be fixed. - let priority_ref = unsafe {(*Self::ptr()).shpr.get_unchecked(usize::from((index - 8) / 4))}; + let priority_ref = unsafe { + (*Self::ptr()) + .shpr + .get_unchecked(usize::from((index - 8) / 4)) + }; let shpr = priority_ref.read(); let prio = (shpr >> (8 * (index % 4))) & 0x0000_00ff; @@ -1008,7 +1016,9 @@ impl SCB { { // NOTE(unsafe): Index is bounded to [11,15] by SystemHandler design. // TODO: Review it after rust-lang/rust/issues/13926 will be fixed. - let priority_ref = (*Self::ptr()).shpr.get_unchecked(usize::from((index - 8) / 4)); + let priority_ref = (*Self::ptr()) + .shpr + .get_unchecked(usize::from((index - 8) / 4)); priority_ref.modify(|value| { let shift = 8 * (index % 4); |