diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/itm.rs | 3 | ||||
| -rw-r--r-- | src/lib.rs | 1 | ||||
| -rw-r--r-- | src/peripheral/cpuid.rs | 1 | ||||
| -rw-r--r-- | src/peripheral/scb.rs | 4 | ||||
| -rw-r--r-- | src/peripheral/syst.rs | 1 | ||||
| -rw-r--r-- | src/register/apsr.rs | 1 | ||||
| -rw-r--r-- | src/register/control.rs | 4 | ||||
| -rw-r--r-- | src/register/faultmask.rs | 1 | ||||
| -rw-r--r-- | src/register/primask.rs | 1 |
9 files changed, 17 insertions, 0 deletions
@@ -9,6 +9,7 @@ use aligned::{Aligned, A4}; use crate::peripheral::itm::Stim; // NOTE assumes that `bytes` is 32-bit aligned +#[allow(clippy::missing_inline_in_public_items)] unsafe fn write_words(stim: &mut Stim, bytes: &[u32]) { let mut p = bytes.as_ptr(); for _ in 0..bytes.len() { @@ -30,6 +31,7 @@ impl<'p> fmt::Write for Port<'p> { /// Writes a `buffer` to the ITM `port` #[allow(clippy::cast_ptr_alignment)] +#[allow(clippy::missing_inline_in_public_items)] #[allow(clippy::transmute_ptr_to_ptr)] pub fn write_all(port: &mut Stim, buffer: &[u8]) { unsafe { @@ -90,6 +92,7 @@ pub fn write_all(port: &mut Stim, buffer: &[u8]) { /// itm::write_aligned(&itm.stim[0], &Aligned(*b"Hello, world!\n")); /// ``` #[allow(clippy::cast_ptr_alignment)] +#[allow(clippy::missing_inline_in_public_items)] #[allow(clippy::transmute_ptr_to_ptr)] pub fn write_aligned(port: &mut Stim, buffer: &Aligned<A4, [u8]>) { unsafe { @@ -34,6 +34,7 @@ #![no_std] #![allow(clippy::identity_op)] #![allow(clippy::missing_safety_doc)] +#![deny(clippy::missing_inline_in_public_items)] extern crate aligned; extern crate bare_metal; diff --git a/src/peripheral/cpuid.rs b/src/peripheral/cpuid.rs index 119cce2..787be5c 100644 --- a/src/peripheral/cpuid.rs +++ b/src/peripheral/cpuid.rs @@ -66,6 +66,7 @@ pub struct RegisterBlock { /// Type of cache to select on CSSELR writes. #[cfg(not(armv6m))] +#[allow(clippy::missing_inline_in_public_items)] #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum CsselrCacheType { /// Select DCache or unified cache diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs index 0e2eefc..9d58b03 100644 --- a/src/peripheral/scb.rs +++ b/src/peripheral/scb.rs @@ -97,6 +97,7 @@ pub struct RegisterBlock { /// FPU access mode #[cfg(has_fpu)] +#[allow(clippy::missing_inline_in_public_items)] #[derive(Clone, Copy, Debug, PartialEq, Eq)] pub enum FpuAccessMode { /// FPU is not accessible @@ -193,6 +194,7 @@ impl SCB { } /// Processor core exceptions (internal interrupts) +#[allow(clippy::missing_inline_in_public_items)] #[derive(Clone, Copy, Debug, Eq, PartialEq)] pub enum Exception { /// Non maskable interrupt @@ -258,6 +260,7 @@ impl Exception { } /// Active exception number +#[allow(clippy::missing_inline_in_public_items)] #[derive(Clone, Copy, Debug, Eq, PartialEq)] pub enum VectActive { /// Thread mode @@ -725,6 +728,7 @@ impl SCB { } /// System handlers, exceptions with configurable priority +#[allow(clippy::missing_inline_in_public_items)] #[derive(Clone, Copy, Debug, Eq, PartialEq)] pub enum SystemHandler { // NonMaskableInt, // priority is fixed diff --git a/src/peripheral/syst.rs b/src/peripheral/syst.rs index abcd00b..69bc488 100644 --- a/src/peripheral/syst.rs +++ b/src/peripheral/syst.rs @@ -18,6 +18,7 @@ pub struct RegisterBlock { } /// SysTick clock source +#[allow(clippy::missing_inline_in_public_items)] #[derive(Clone, Copy, Debug, PartialEq, Eq)] pub enum SystClkSource { /// Core-provided clock diff --git a/src/register/apsr.rs b/src/register/apsr.rs index 0e54022..97a9f01 100644 --- a/src/register/apsr.rs +++ b/src/register/apsr.rs @@ -1,6 +1,7 @@ //! Application Program Status Register /// Application Program Status Register +#[allow(clippy::missing_inline_in_public_items)] #[derive(Clone, Copy, Debug)] pub struct Apsr { bits: u32, diff --git a/src/register/control.rs b/src/register/control.rs index ab33029..07b26c3 100644 --- a/src/register/control.rs +++ b/src/register/control.rs @@ -1,6 +1,7 @@ //! Control register /// Control register +#[allow(clippy::missing_inline_in_public_items)] #[derive(Clone, Copy, Debug)] pub struct Control { bits: u32, @@ -81,6 +82,7 @@ impl Control { } /// Thread mode privilege level +#[allow(clippy::missing_inline_in_public_items)] #[derive(Clone, Copy, Debug, Eq, PartialEq)] pub enum Npriv { /// Privileged @@ -104,6 +106,7 @@ impl Npriv { } /// Currently active stack pointer +#[allow(clippy::missing_inline_in_public_items)] #[derive(Clone, Copy, Debug, Eq, PartialEq)] pub enum Spsel { /// MSP is the current stack pointer @@ -127,6 +130,7 @@ impl Spsel { } /// Whether context floating-point is currently active +#[allow(clippy::missing_inline_in_public_items)] #[derive(Clone, Copy, Debug, Eq, PartialEq)] pub enum Fpca { /// Floating-point context active. diff --git a/src/register/faultmask.rs b/src/register/faultmask.rs index 6fa09af..811385f 100644 --- a/src/register/faultmask.rs +++ b/src/register/faultmask.rs @@ -1,6 +1,7 @@ //! Fault Mask Register /// All exceptions are ... +#[allow(clippy::missing_inline_in_public_items)] #[derive(Clone, Copy, Debug, Eq, PartialEq)] pub enum Faultmask { /// Active diff --git a/src/register/primask.rs b/src/register/primask.rs index 612abc5..018c45b 100644 --- a/src/register/primask.rs +++ b/src/register/primask.rs @@ -1,6 +1,7 @@ //! Priority mask register /// All exceptions with configurable priority are ... +#[allow(clippy::missing_inline_in_public_items)] #[derive(Clone, Copy, Debug, Eq, PartialEq)] pub enum Primask { /// Active |