diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/delay.rs | 22 | ||||
| -rw-r--r-- | src/interrupt.rs | 11 | ||||
| -rw-r--r-- | src/lib.rs | 2 | ||||
| -rw-r--r-- | src/peripheral/dcb.rs | 17 | ||||
| -rw-r--r-- | src/peripheral/dwt.rs | 117 | ||||
| -rw-r--r-- | src/peripheral/icb.rs | 6 | ||||
| -rw-r--r-- | src/peripheral/mod.rs | 8 | ||||
| -rw-r--r-- | src/peripheral/scb.rs | 10 |
8 files changed, 140 insertions, 53 deletions
diff --git a/src/delay.rs b/src/delay.rs index 8ed1fea..66a63bf 100644 --- a/src/delay.rs +++ b/src/delay.rs @@ -6,7 +6,7 @@ use embedded_hal::blocking::delay::{DelayMs, DelayUs}; /// System timer (SysTick) as a delay provider. pub struct Delay { syst: SYST, - ahb_frequency: u32, + frequency: u32, } impl Delay { @@ -14,13 +14,19 @@ impl Delay { /// /// `ahb_frequency` is a frequency of the AHB bus in Hz. #[inline] - pub fn new(mut syst: SYST, ahb_frequency: u32) -> Self { - syst.set_clock_source(SystClkSource::Core); + pub fn new(syst: SYST, ahb_frequency: u32) -> Self { + Self::with_source(syst, ahb_frequency, SystClkSource::Core) + } - Delay { - syst, - ahb_frequency, - } + /// Configures the system timer (SysTick) as a delay provider + /// with a clock source. + /// + /// `frequency` is the frequency of your `clock_source` in Hz. + #[inline] + pub fn with_source(mut syst: SYST, frequency: u32, clock_source: SystClkSource) -> Self { + syst.set_clock_source(clock_source); + + Delay { syst, frequency } } /// Releases the system timer (SysTick) resource. @@ -32,7 +38,7 @@ impl Delay { /// Delay using the Cortex-M systick for a certain duration, in µs. #[allow(clippy::missing_inline_in_public_items)] pub fn delay_us(&mut self, us: u32) { - let ticks = (u64::from(us)) * (u64::from(self.ahb_frequency)) / 1_000_000; + let ticks = (u64::from(us)) * (u64::from(self.frequency)) / 1_000_000; let full_cycles = ticks >> 24; if full_cycles > 0 { diff --git a/src/interrupt.rs b/src/interrupt.rs index 0fd1284..68719ec 100644 --- a/src/interrupt.rs +++ b/src/interrupt.rs @@ -1,6 +1,6 @@ //! Interrupts -pub use bare_metal::{CriticalSection, Mutex, Nr}; +pub use bare_metal::{CriticalSection, Mutex}; /// Trait for enums of external interrupt numbers. /// @@ -23,15 +23,6 @@ pub unsafe trait InterruptNumber: Copy { fn number(self) -> u16; } -/// Implement InterruptNumber for the old bare_metal::Nr trait. -/// This implementation is for backwards compatibility only and will be removed in cortex-m 0.8. -unsafe impl<T: Nr + Copy> InterruptNumber for T { - #[inline] - fn number(self) -> u16 { - self.nr() as u16 - } -} - /// Disables all interrupts #[inline] pub fn disable() { @@ -76,6 +76,8 @@ // - A generated #[derive(Debug)] function (in which case the attribute needs // to be applied to the struct). #![deny(clippy::missing_inline_in_public_items)] +// Don't warn about feature(asm) being stable on Rust >= 1.59.0 +#![allow(stable_features)] extern crate bare_metal; extern crate volatile_register; diff --git a/src/peripheral/dcb.rs b/src/peripheral/dcb.rs index 056150b..ef879ac 100644 --- a/src/peripheral/dcb.rs +++ b/src/peripheral/dcb.rs @@ -6,6 +6,7 @@ use crate::peripheral::DCB; use core::ptr; const DCB_DEMCR_TRCENA: u32 = 1 << 24; +const DCB_DEMCR_MON_EN: u32 = 1 << 16; /// Register block #[repr(C)] @@ -46,6 +47,22 @@ impl DCB { } } + /// Enables the [`DebugMonitor`](crate::peripheral::scb::Exception::DebugMonitor) exception + #[inline] + pub fn enable_debug_monitor(&mut self) { + unsafe { + self.demcr.modify(|w| w | DCB_DEMCR_MON_EN); + } + } + + /// Disables the [`DebugMonitor`](crate::peripheral::scb::Exception::DebugMonitor) exception + #[inline] + pub fn disable_debug_monitor(&mut self) { + unsafe { + self.demcr.modify(|w| w & !DCB_DEMCR_MON_EN); + } + } + /// Is there a debugger attached? (see note) /// /// Note: This function is [reported not to diff --git a/src/peripheral/dwt.rs b/src/peripheral/dwt.rs index 11dd545..db0398d 100644 --- a/src/peripheral/dwt.rs +++ b/src/peripheral/dwt.rs @@ -82,11 +82,17 @@ bitfield! { #[repr(C)] #[derive(Copy, Clone)] /// Comparator FUNCTIONn register. + /// + /// See C1.8.17 "Comparator Function registers, DWT_FUNCTIONn" pub struct Function(u32); u8, function, set_function: 3, 0; emitrange, set_emitrange: 5; cycmatch, set_cycmatch: 7; datavmatch, set_datavmatch: 8; + lnk1ena, set_lnk1ena: 9; + u8, datavsize, set_datavsize: 11, 10; + u8, datavaddr0, set_datavaddr0: 15, 12; + u8, datavaddr1, set_datavaddr1: 19, 16; matched, _: 24; } @@ -114,10 +120,13 @@ impl DWT { } /// Returns `true` if the implementation supports a cycle counter - #[cfg(not(armv6m))] #[inline] pub fn has_cycle_counter(&self) -> bool { - !self.ctrl.read().nocyccnt() + #[cfg(not(armv6m))] + return !self.ctrl.read().nocyccnt(); + + #[cfg(armv6m)] + return false; } /// Returns `true` if the implementation the profiling counters @@ -318,15 +327,15 @@ impl DWT { /// Whether the comparator should match on read, write or read/write operations. #[derive(Debug, Eq, PartialEq, Copy, Clone)] pub enum AccessType { - /// Generate packet only when matched adress is read from. + /// Generate packet only when matched address is read from. ReadOnly, - /// Generate packet only when matched adress is written to. + /// Generate packet only when matched address is written to. WriteOnly, - /// Generate packet when matched adress is both read from and written to. + /// Generate packet when matched address is both read from and written to. ReadWrite, } -/// The sequence of packet(s) that should be emitted on comparator match. +/// The sequence of packet(s) or events that should be emitted/generated on comparator match. #[derive(Debug, Eq, PartialEq, Copy, Clone)] pub enum EmitOption { /// Emit only trace data value packet. @@ -341,6 +350,14 @@ pub enum EmitOption { AddressData, /// Emit trace PC value and data value packets. PCData, + /// Generate a watchpoint debug event. Either halts execution or fires a `DebugMonitor` exception. + /// + /// See more in section "Watchpoint debug event generation" page C1-729. + WatchpointDebugEvent, + /// Generate a `CMPMATCH[N]` event. + /// + /// See more in section "CMPMATCH[N] event generation" page C1-730. + CompareMatchEvent, } /// Settings for address matching @@ -356,12 +373,27 @@ pub struct ComparatorAddressSettings { pub access_type: AccessType, } +/// Settings for cycle count matching +#[derive(Debug, Eq, PartialEq, Copy, Clone)] +pub struct CycleCountSettings { + /// The function selection used. + /// See Table C1-15 for DWT cycle count comparison functions. + pub emit: EmitOption, + /// The cycle count value to compare against. + pub compare: u32, +} + /// The available functions of a DWT comparator. #[derive(Debug, Eq, PartialEq, Copy, Clone)] #[non_exhaustive] pub enum ComparatorFunction { /// Compare accessed memory addresses. Address(ComparatorAddressSettings), + /// Compare cycle count & target value. + /// + /// **NOTE**: only supported by comparator 0 and if the HW supports the cycle counter. + /// Check [`DWT::has_cycle_counter`] for support. See C1.8.1 for more details. + CycleCount(CycleCountSettings), } /// Possible error values returned on [Comparator::configure]. @@ -377,7 +409,7 @@ impl Comparator { #[allow(clippy::missing_inline_in_public_items)] pub fn configure(&self, settings: ComparatorFunction) -> Result<(), DwtError> { match settings { - ComparatorFunction::Address(settings) => unsafe { + ComparatorFunction::Address(settings) => { // FUNCTION, EMITRANGE // See Table C1-14 let (function, emit_range) = match (&settings.access_type, &settings.emit) { @@ -385,38 +417,77 @@ impl Comparator { (AccessType::ReadOnly, EmitOption::Address) => (0b1100, true), (AccessType::ReadOnly, EmitOption::AddressData) => (0b1110, true), (AccessType::ReadOnly, EmitOption::PCData) => (0b1110, false), + (AccessType::ReadOnly, EmitOption::WatchpointDebugEvent) => (0b0101, false), + (AccessType::ReadOnly, EmitOption::CompareMatchEvent) => (0b1001, false), (AccessType::WriteOnly, EmitOption::Data) => (0b1101, false), (AccessType::WriteOnly, EmitOption::Address) => (0b1101, true), (AccessType::WriteOnly, EmitOption::AddressData) => (0b1111, true), (AccessType::WriteOnly, EmitOption::PCData) => (0b1111, false), + (AccessType::WriteOnly, EmitOption::WatchpointDebugEvent) => (0b0110, false), + (AccessType::WriteOnly, EmitOption::CompareMatchEvent) => (0b1010, false), (AccessType::ReadWrite, EmitOption::Data) => (0b0010, false), (AccessType::ReadWrite, EmitOption::Address) => (0b0001, true), (AccessType::ReadWrite, EmitOption::AddressData) => (0b0010, true), (AccessType::ReadWrite, EmitOption::PCData) => (0b0011, false), + (AccessType::ReadWrite, EmitOption::WatchpointDebugEvent) => (0b0111, false), + (AccessType::ReadWrite, EmitOption::CompareMatchEvent) => (0b1011, false), (AccessType::ReadWrite, EmitOption::PC) => (0b0001, false), (_, EmitOption::PC) => return Err(DwtError::InvalidFunction), }; - self.function.modify(|mut r| { - r.set_function(function); - r.set_emitrange(emit_range); - - // don't compare data value - r.set_datavmatch(false); - - // don't compare cycle counter value - // NOTE: only needed for comparator 0, but is SBZP. - r.set_cycmatch(false); - - r - }); + unsafe { + self.function.modify(|mut r| { + r.set_function(function); + r.set_emitrange(emit_range); + // don't compare data value + r.set_datavmatch(false); + // don't compare cycle counter value + // NOTE: only needed for comparator 0, but is SBZP. + r.set_cycmatch(false); + // SBZ as needed, see Page 784/C1-724 + r.set_datavsize(0); + r.set_datavaddr0(0); + r.set_datavaddr1(0); + + r + }); + + self.comp.write(settings.address); + self.mask.write(settings.mask); + } + } + ComparatorFunction::CycleCount(settings) => { + let function = match &settings.emit { + EmitOption::PCData => 0b0001, + EmitOption::WatchpointDebugEvent => 0b0100, + EmitOption::CompareMatchEvent => 0b1000, + _ => return Err(DwtError::InvalidFunction), + }; - self.comp.write(settings.address); - self.mask.write(settings.mask); - }, + unsafe { + self.function.modify(|mut r| { + r.set_function(function); + // emit_range is N/A for cycle count compare + r.set_emitrange(false); + // don't compare data + r.set_datavmatch(false); + // compare cyccnt + r.set_cycmatch(true); + // SBZ as needed, see Page 784/C1-724 + r.set_datavsize(0); + r.set_datavaddr0(0); + r.set_datavaddr1(0); + + r + }); + + self.comp.write(settings.compare); + self.mask.write(0); // SBZ, see Page 784/C1-724 + } + } } Ok(()) diff --git a/src/peripheral/icb.rs b/src/peripheral/icb.rs index 9b29655..e1de33b 100644 --- a/src/peripheral/icb.rs +++ b/src/peripheral/icb.rs @@ -1,6 +1,6 @@ //! Implementation Control Block -#[cfg(any(armv7m, armv8m, target_arch = "x86_64"))] +#[cfg(any(armv7m, armv8m, native))] use volatile_register::RO; use volatile_register::RW; @@ -12,12 +12,12 @@ pub struct RegisterBlock { /// The bottom four bits of this register give the number of implemented /// interrupt lines, divided by 32. So a value of `0b0010` indicates 64 /// interrupts. - #[cfg(any(armv7m, armv8m, target_arch = "x86_64"))] + #[cfg(any(armv7m, armv8m, native))] pub ictr: RO<u32>, /// The ICTR is not defined in the ARMv6-M Architecture Reference manual, so /// we replace it with this. - #[cfg(not(any(armv7m, armv8m, target_arch = "x86_64")))] + #[cfg(not(any(armv7m, armv8m, native)))] _reserved: u32, /// Auxiliary Control Register diff --git a/src/peripheral/mod.rs b/src/peripheral/mod.rs index 081aa0a..d1e119f 100644 --- a/src/peripheral/mod.rs +++ b/src/peripheral/mod.rs @@ -71,8 +71,8 @@ pub mod dcb; pub mod dwt; #[cfg(not(armv6m))] pub mod fpb; -// NOTE(target_arch) is for documentation purposes -#[cfg(any(has_fpu, target_arch = "x86_64"))] +// NOTE(native) is for documentation purposes +#[cfg(any(has_fpu, native))] pub mod fpu; pub mod icb; #[cfg(all(not(armv6m), not(armv8m_base)))] @@ -411,7 +411,7 @@ pub struct FPU { unsafe impl Send for FPU {} -#[cfg(any(has_fpu, target_arch = "x86_64"))] +#[cfg(any(has_fpu, native))] impl FPU { /// Pointer to the register block pub const PTR: *const fpu::RegisterBlock = 0xE000_EF30 as *const _; @@ -423,7 +423,7 @@ impl FPU { } } -#[cfg(any(has_fpu, target_arch = "x86_64"))] +#[cfg(any(has_fpu, native))] impl ops::Deref for FPU { type Target = self::fpu::RegisterBlock; diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs index 6c16149..eeea0c5 100644 --- a/src/peripheral/scb.rs +++ b/src/peripheral/scb.rs @@ -182,7 +182,7 @@ impl SCB { 5 => VectActive::Exception(Exception::BusFault), #[cfg(not(armv6m))] 6 => VectActive::Exception(Exception::UsageFault), - #[cfg(any(armv8m, target_arch = "x86_64"))] + #[cfg(any(armv8m, native))] 7 => VectActive::Exception(Exception::SecureFault), 11 => VectActive::Exception(Exception::SVCall), #[cfg(not(armv6m))] @@ -218,7 +218,7 @@ pub enum Exception { UsageFault, /// Secure fault interrupt (only on ARMv8-M) - #[cfg(any(armv8m, target_arch = "x86_64"))] + #[cfg(any(armv8m, native))] SecureFault, /// SV call interrupt @@ -250,7 +250,7 @@ impl Exception { Exception::BusFault => -11, #[cfg(not(armv6m))] Exception::UsageFault => -10, - #[cfg(any(armv8m, target_arch = "x86_64"))] + #[cfg(any(armv8m, native))] Exception::SecureFault => -9, Exception::SVCall => -5, #[cfg(not(armv6m))] @@ -293,7 +293,7 @@ impl VectActive { 5 => VectActive::Exception(Exception::BusFault), #[cfg(not(armv6m))] 6 => VectActive::Exception(Exception::UsageFault), - #[cfg(any(armv8m, target_arch = "x86_64"))] + #[cfg(any(armv8m, native))] 7 => VectActive::Exception(Exception::SecureFault), 11 => VectActive::Exception(Exception::SVCall), #[cfg(not(armv6m))] @@ -934,7 +934,7 @@ pub enum SystemHandler { UsageFault = 6, /// Secure fault interrupt (only on ARMv8-M) - #[cfg(any(armv8m, target_arch = "x86_64"))] + #[cfg(any(armv8m, native))] SecureFault = 7, /// SV call interrupt |