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2019-03-13Merge #135v0.6.0Gravatar bors[bot] 2-2/+20
135: Prepare release v0.6.0 r=korken89 a=adamgreig :tada: Co-authored-by: Adam Greig <adam@adamgreig.com>
2019-03-12v0.6.0Gravatar Adam Greig 2-2/+20
2019-03-12Merge #106Gravatar bors[bot] 3-6/+54
106: Stir register and debugger check r=adamgreig a=thenewwazoo Adds support for requesting an interrupt via the STIR register and checking whether a debugger is attached. Co-authored-by: Brandon Matthews <bmatthews@zipcar.com> Co-authored-by: Brandon Matthews <bmatthews@optimaltour.us>
2019-03-12Merge #127Gravatar bors[bot] 2-1/+29
127: Cortex M0(+) DWT fixes r=adamgreig a=korken89 The current DWT setup has a lot of registers that are not available in Cortex-M0(+), fixes are added here. Co-authored-by: Emil Fresk <emil.fresk@gmail.com>
2019-03-12Fix STIR register test, remove armv6m-related offsets in NVICGravatar Brandon Matthews 1-5/+2
2019-03-12Merge #97Gravatar bors[bot] 2-2/+2
97: Rename `shcrs` to `shcsr` in `scb::RegisterBlock` r=adamgreig a=rajivr Commit `c290aa4e` introduced `shcrs` field to `scb::RegisterBlock`. In CMSIS, this field is `shcsr`. https://github.com/ARM-software/CMSIS_5/blob/5.3.0/CMSIS/Core/Include/core_cm4.h#L449 This patch changes `shcrs` to `shcsr`. Signed-off-by: Rajiv Ranganath <rajiv.ranganath@gmail.com> Co-authored-by: Rajiv Ranganath <rajiv.ranganath@gmail.com>
2019-03-12Merge #126Gravatar bors[bot] 2-4/+4
126: Upgrade to aligned 0.3 r=adamgreig a=rnestler Co-authored-by: Raphael Nestler <raphael.nestler@gmail.com>
2019-03-12Update is_debugger_attached so as not to clear S_RESET_ST and S_RETIRE_STGravatar Brandon Matthews 1-8/+14
2019-03-12Fix rebase syntax error; disable STIR test on armv6mGravatar Brandon Matthews 2-0/+2
2019-03-12Expand is_debugger_attached noteGravatar Brandon Matthews 1-2/+5
2019-03-12Add explanatory note about C_DEBUGENGravatar Brandon Matthews 1-3/+9
2019-03-12Add note that NVIC::request is not available on armv6mGravatar Brandon Matthews 1-0/+2
2019-03-12Exclude unused import and elide nvic::request for armv6mGravatar Brandon Matthews 1-2/+3
2019-03-12Add STIR register address testGravatar Brandon Matthews 1-0/+1
2019-03-12Add support for debugger checkGravatar Brandon Matthews 1-2/+6
2019-03-12Add STIR register to NVIC peripheralGravatar Brandon Matthews 1-1/+27
2019-01-19Merge #130Gravatar bors[bot] 3-0/+7
130: Add thumbv8m main. r=adamgreig a=nezza rustup supports the `thumbv8m.main-none-eabi` target, this adds support for `thumbv8m.main-none-eabi` to cortex-m. Related PRs: https://github.com/rust-embedded/cortex-m-semihosting/pull/28 https://github.com/rust-embedded/cortex-m-rt/pull/167 Co-authored-by: Thomas Roth <thomas.roth@leveldown.de>
2019-01-16Add thumbv8m.main-none-eabi to Travis.Gravatar Thomas Roth 1-0/+4
2019-01-16Add thumbv8m main.Gravatar Thomas Roth 2-0/+3
2019-01-12Merge #129Gravatar bors[bot] 1-1/+4
129: add team e-mail to authors r=therealprof a=japaric Co-authored-by: Jorge Aparicio <jorge@japaric.io>
2019-01-12add team e-mail to authorsGravatar Jorge Aparicio 1-1/+4
2018-12-15Fix for error in TravisGravatar Emil Fresk 1-1/+3
2018-12-15Test fixesGravatar Emil Fresk 1-0/+8
2018-12-15Fixes for DWT on Cortex-M0Gravatar Emil Fresk 1-0/+18
2018-12-09Upgrade to aligned 0.3Gravatar Raphael Nestler 2-4/+4
2018-11-20Merge #124Gravatar bors[bot] 1-0/+18
124: Add api to set SLEEPONEXIT bit in SCR register r=korken89 a=simonvandel Co-authored-by: Simon Vandel Sillesen <simon.vandel@gmail.com>
2018-11-20Add api to set SLEEPONEXIT bit in SCR registerGravatar Simon Vandel Sillesen 1-0/+18
2018-11-03Merge #123Gravatar bors[bot] 3-0/+6
123: add thumbv8m baseline support r=therealprof a=evq Co-authored-by: eV <ev@7pr.xyz>
2018-11-03add thumbv8m baseline supportGravatar eV 3-0/+6
2018-10-27Merge #121v0.5.8Gravatar bors[bot] 2-2/+24
121: v0.5.8 r=therealprof a=japaric required to make a release we can publish now or wait for #120 Co-authored-by: Jorge Aparicio <jorge@japaric.io>
2018-10-27{,un}pend -> {unpend,pend}Gravatar Jorge Aparicio 1-1/+1
2018-10-27incorporate #120 into the CHANGELOGGravatar Jorge Aparicio 1-0/+8
2018-10-27v0.5.8Gravatar Jorge Aparicio 2-2/+16
required to make a release we can publish now or wait for #120
2018-10-27Merge #120Gravatar bors[bot] 1-5/+25
120: deprecate NVIC.{clear,set}_pending in favor of NVIC::{un,}pend r=therealprof a=japaric NVIC::{un,}pend are static methods that don't require an instance of NVIC to be invoked. Rationale: These operations perform writes to stateless registers so they can *not* result in data races. More tricky is the question of whether letting the user call these from any execution context without any critical section or other means of synchronization can result in memory unsafety when used in conjunction with methods like NVIC.{get,set}_priority that do require an instance of NVIC. I can't foresee any trouble given that these methods (e.g. pend and set_priority) operate on different registers. Co-authored-by: Jorge Aparicio <jorge@japaric.io>
2018-10-27deprecate NVIC.{clear,set}_pending in favor of NVIC::{un,}pendGravatar Jorge Aparicio 1-5/+25
NVIC::{un,}pend are static methods that don't require an instance of NVIC to be invoked.
2018-10-26Merge #118Gravatar bors[bot] 1-1/+2
118: Add additional meta data to improve crate experience r=therealprof a=Nicoretti * Add readme setting, so README.md is shown on https://crates.io/ Co-authored-by: Nicola Coretti <nicola.coretti@esrlabs.com>
2018-10-26Merge #117Gravatar bors[bot] 5-2/+121
117: add high level API to set priority of system handlers r=therealprof a=japaric needed for cortex-m-rtfm v0.4.x (it makes my life easier / it makes it easier to support ARMv6-M) r? @rust-embedded/cortex-m (anyone) Co-authored-by: Jorge Aparicio <jorge@japaric.io>
2018-10-26deny warnings only on nightlyGravatar Jorge Aparicio 2-1/+4
lints have changed between nightly and stable
2018-10-26remove hidden variantGravatar Jorge Aparicio 1-5/+0
it was there to maybe support adding DebugMonitor in the future but it has already been added
2018-10-26add DebugMonitor variant to SystemHandlerGravatar Jorge Aparicio 1-2/+6
2018-10-26fix shiftGravatar Jorge Aparicio 1-2/+2
2018-10-26Add additional meta data to improve crate experienceGravatar Nicola Coretti 1-1/+2
* Add readme setting, so README.md is shown on https://crates.io/
2018-10-24fix warningGravatar Jorge Aparicio 1-1/+0
2018-10-24add high level API to set priority of system handlersGravatar Jorge Aparicio 2-0/+118
2018-10-03Merge #116Gravatar bors[bot] 1-10/+38
116: Add SysTick flags r=adamgreig a=qwerty19106 CMSIS core headers contains SCB_ICSR_PENDSVSET_*** and SCB_ICSR_PENDSTSET_*** definitions, which I need in my projects. In CMSIS it is used to check, set and clear this flags (rtx_core_cm.h and os_systick.c). I suggest adding it to scb.rs. I put initial commit, but I need help to add compiler barriers where its are needed. For details, see CMSIS: [CMSIS_5/CMSIS/Core/Include/core_cm3.h](https://github.com/ARM-software/CMSIS_5/blob/develop/CMSIS/Core/Include/core_cm3.h) (or other core_cm{X}.h) [CMSIS_5/CMSIS/RTOS2/RTX/Source/rtx_core_cm.h)](https://github.com/ARM-software/CMSIS_5/blob/develop/CMSIS/RTOS2/RTX/Source/rtx_core_cm.h) [CMSIS_5/CMSIS/RTOS2/Source/os_systick.c)](https://github.com/ARM-software/CMSIS_5/blob/develop/CMSIS/RTOS2/Source/os_systick.c) FIX: I have not seen that PENDSV is already added. I review PENDST code to be like PENDSV. Co-authored-by: qwerty19106 <qwerty19106@gmail.com>
2018-10-01Autoformat scb.rs by rustfmtGravatar qwerty19106 1-13/+14
2018-10-01Remove blank lineGravatar qwerty19106 1-1/+0
2018-10-01Fix function names and remove exclusive accessGravatar qwerty19106 1-3/+3
2018-09-24Fix duplicate PendSV.Gravatar qwerty19106 1-56/+28
2018-09-24Added Pending SV (Service Call) and SysTick flagsGravatar qwerty19106 1-0/+56
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