aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2019-10-29Merge #168Gravatar bors[bot] 1-0/+4
168: Test thumbv8m.base on Travis CI r=korken89 a=JJJollyjim This will fail until #155 is resolved Co-authored-by: Jamie McClymont <jamie@kwiius.com>
2019-10-29Merge #174Gravatar bors[bot] 7-9/+16
174: Enable clippy in CI r=thejpster a=m-ou-se Co-authored-by: Mara Bos <m-ou.se@m-ou.se>
2019-10-29Enable clippy in CI.Gravatar Mara Bos 1-0/+9
2019-10-29Make clippy happy, again.Gravatar Mara Bos 6-9/+7
2019-10-29Merge #167Gravatar bors[bot] 3-3/+29
167: Deprecate basepri/basepri_max on thumbv8m.base r=korken89 a=JJJollyjim First step in resolving #155 Co-authored-by: Jamie McClymont <jamie@kwiius.com>
2019-10-29Add another missing #[inline].Gravatar Mara Bos 1-0/+1
2019-10-29Add `#[inline]` to some more functions.Gravatar Mara Bos 5-0/+27
Now the only public non-inline functions left are: - write_all - write_aligned - All (derived) Debug implementations (Checked using Clippy's missing_inline_in_public_items lint.)
2019-10-29Add `#[inline]` to lots of trivial functions.Gravatar Mara Bos 8-0/+75
2019-10-28Merge #172Gravatar bors[bot] 11-49/+53
172: Make Clippy happy. r=therealprof a=m-ou-se Co-authored-by: Mara Bos <m-ou.se@m-ou.se>
2019-10-16Merge #173Gravatar bors[bot] 1-0/+9
173: add a safe method to software unlock the DWT r=therealprof a=japaric today the alternative is an unsafe write to the LAR register Co-authored-by: Jorge Aparicio <jorge@japaric.io>
2019-10-15add a safe method to software unlock the DWTGravatar Jorge Aparicio 1-0/+9
today the alternative is an unsafe write to the LAR register
2019-10-09Make Clippy happy.Gravatar Mara Bos 11-49/+53
2019-09-22Changelog entry for thumbv8.base register deprecationsGravatar Jamie McClymont 1-0/+4
2019-09-21Test thumbv8m.base on travisGravatar Jamie McClymont 1-0/+4
2019-09-21Deprecate nonexistent registers on thumbv8m.baseGravatar Jamie McClymont 2-3/+25
First step in resolving #155
2019-09-13Merge #164Gravatar bors[bot] 9-5/+86
164: Allow writing to the CONTROL register r=adamgreig a=jonas-schievink This allows entering unprivileged mode. Part of https://github.com/rust-embedded/cortex-m/issues/58 Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
2019-09-10Merge #165Gravatar bors[bot] 2-10/+10
165: Slightly improve the bash scripts r=adamgreig a=jonas-schievink cf. https://github.com/rust-embedded/cortex-m-rt/pull/204 Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
2019-09-10 Address shellcheck warningsGravatar Jonas Schievink 1-8/+8
2019-09-10Use a more robust shebangGravatar Jonas Schievink 2-2/+2
2019-09-10Make some trivial functions eligible for inliningGravatar Jonas Schievink 1-0/+14
2019-09-08Remove unnecessary unsafe blockGravatar Jonas Schievink 1-1/+1
2019-09-08Fix errors and warningsGravatar Jonas Schievink 1-16/+14
2019-09-06Allow writing to the CONTROL registerGravatar Jonas Schievink 9-5/+74
2019-08-26Merge #163Gravatar bors[bot] 1-1/+1
163: fix changelog link for v0.6.1 r=korken89 a=TDHolmes The v0.6.1 link is broken and v0.6.0 links to v0.6.1 changes. Fix the typo to fix that Co-authored-by: Tyler Holmes <tylerdanielholmes@gmail.com>
2019-08-25fix changelog link for v0.6.1Gravatar Tyler Holmes 1-1/+1
2019-08-21Merge #162v0.6.1Gravatar bors[bot] 2-2/+22
162: 0.6.1 release r=adamgreig a=korken89 There has been a lot of work, time to ship it :) Co-authored-by: Emil Fresk <emil.fresk@gmail.com>
2019-08-210.6.1 releaseGravatar Emil Fresk 2-2/+22
2019-08-12Merge #161Gravatar bors[bot] 8-2/+138
161: Add {M,P}SPLIM access routines found on ARMv8-M mainline extension r=thejpster a=aurabindo I'd like to add better v8-M support. I'm not sure if this is PR has an optimal way of handling arch extension. As per ARMv8 Architecture reference manual, the baseline variant is not compatible with ARMv7-M. Only the main extension brings backward compatibility with v7-M. This PR adds support for accessing MSPLIM and PSPLIM registers, and missing binaries for `thumbv8m.main-none-eabihf` architecture. Co-authored-by: Aurabindo Jayamohanan <mail@aurabindo.in>
2019-08-11Add {M,P}SPLIM access routines found on ARMv8-MGravatar Aurabindo Jayamohanan 8-2/+138
Signed-off-by: Aurabindo Jayamohanan <mail@aurabindo.in>
2019-07-29Merge #160Gravatar bors[bot] 17-76/+62
160: Update for 2018 edition r=korken89 a=adamgreig Co-authored-by: Adam Greig <adam@adamgreig.com>
2019-07-29Fix missing `crate::`Gravatar Adam Greig 2-2/+2
2019-07-29Update for 2018 editionGravatar Adam Greig 15-74/+60
2019-07-28Merge #159Gravatar bors[bot] 4-8/+27
159: Define MSRV to be 1.31.0 and unconditionally use const-fn r=therealprof a=adamgreig As per https://github.com/rust-embedded/wg/blob/master/ops/msrv.md we should have a defined MSRV for this crate. This PR proposes setting it to 1.31 to allow use of `const-fn` from bare-metal by default, and updates `Cargo.toml` accordingly. It also sets the edition to 2018, permitted by an MSRV of 1.31. Since this PR _introduces_ an MSRV I propose it not requiring a semver bump, and we instead would look to release this change as `0.6.1`. Closes #153. Co-authored-by: Adam Greig <adam@ael.co.uk> Co-authored-by: Adam Greig <adam@adamgreig.com>
2019-07-27Defer edition-2018 for another PRGravatar Adam Greig 1-1/+0
2019-07-24Re-add unused const-fn function to preserve backwards compatibilityGravatar Adam Greig 1-0/+2
2019-07-24Define MSRV to be 1.31.0 and unconditionally use const-fnGravatar Adam Greig 4-8/+26
2019-07-04Merge #152Gravatar bors[bot] 7-1/+2
152: Fix __delay asm function for the thumbv6m-none-eabi target r=therealprof a=Disasm Before: ``` 00000000 <__delay>: 0: 46c0 nop ; (mov r8, r8) 2: 3801 subs r0, #1 4: d1fe bne.n 0 <__delay> 4: R_ARM_THM_JUMP8 __delay 6: 4770 bx lr ``` After: ``` 00000000 <__delay>: 0: 46c0 nop ; (mov r8, r8) 2: 3801 subs r0, #1 4: d1fc bne.n 0 <__delay> 6: 4770 bx lr ``` Closes https://github.com/rust-embedded/cortex-m/issues/125 Co-authored-by: Vadim Kaushan <admin@disasm.info>
2019-07-04Regenerate binariesGravatar Vadim Kaushan 6-0/+0
2019-07-04Fix __delay for the thumbv6m-none-eabi targetGravatar Vadim Kaushan 1-1/+2
2019-06-19Merge #150Gravatar bors[bot] 1-5/+26
150: add NVIC::{mask,unmask} r=therealprof a=japaric these are the "static method" (methods that don't take `self`) versions of NVIC::{enable,disable} in the same vein as the existing NVIC::{pend,unpend} this commit also deprecates the existing NVIC::{enable,disable} methods and notes that NVIC::enable is unsound because it should be an `unsafe` method (like interrupt::enable and basepri::write, it can break critical sections) but it's marked as safe. Its replacement, NVIC::unmask, has the correct unsafety setting: it's an `unsafe` function. Co-authored-by: Jorge Aparicio <jorge@japaric.io>
2019-06-19add NVIC::{mask,unmask}Gravatar Jorge Aparicio 1-5/+26
these are the "static method" (methods that don't take `self`) versions of NVIC::{enable,disable} in the same vein as the existing NVIC::{pend,unpend} this commit also deprecates the existing NVIC::{enable,disable} methods and notes that NVIC::enable is unsound because it should be an `unsafe` method (like interrupt::enable and basepri::write, it can break critical sections) but it's marked as safe. Its replacement, NVIC::unmask, has the correct unsafety setting: it's an `unsafe` function.
2019-06-15Merge #147Gravatar bors[bot] 1-2/+0
147: Remove debug_assert from Peripherals::steal r=thejpster a=mvirkkunen This is the same change as https://github.com/rust-embedded/svd2rust/pull/238, except for the one bit that isn't generated by svd2rust. There was a decent amount of discussion about this over at that issue, and to me it makes sense to change this here as well. It's `unsafe`, so let the user decide if they want to use it. Co-authored-by: Matti Virkkunen <mvirkkunen@gmail.com>
2019-06-13Remove debug_assert from Peripherals::stealGravatar Matti Virkkunen 1-2/+0
2019-06-06Merge #140Gravatar bors[bot] 1-0/+1
140: Cargo.toml: Add `links = "cortex-m"` r=therealprof a=jonas-schievink This prevents linking multiple versions of `cortex-m` together, which would be unsound. Currently it uses a `#[no_mangle]` static for this, which isn't always reliable. Fixes #137 Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
2019-04-24Merge #141Gravatar bors[bot] 3-2/+3
141: Derive Debug, PartialEq and Eq for more types r=therealprof a=jonas-schievink Closes #28 Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
2019-04-24Derive Debug, PartialEq and Eq for more typesGravatar Jonas Schievink 3-2/+3
2019-04-24Cargo.toml: Add `links = "cortex-m"`Gravatar Jonas Schievink 1-0/+1
2019-04-14Merge #138Gravatar bors[bot] 1-0/+20
138: scb: add static version of system_reset as sys_reset r=korken89 a=hdhoang As suggested in https://github.com/ah-/anne-key/pull/94. I branched this off v0.5.8 to verify the function in that PR, and against rtfm v0.3 in https://github.com/hdhoang/anne-key/commit/d6fb831cbbb46bc10a6184b78bf13e00245234d6 I have cloned the body of `system_reset`, do you think we should call one from the other (e.g. ignoring `self` in `system_reset`, or stealing `Peripherals` in `system_reset2`)? Co-authored-by: Hoàng Đức Hiếu <code@hdhoang.space>
2019-04-13deprecate system_reset in favor of static sys_resetGravatar Hoàng Đức Hiếu 1-3/+2
2019-03-21scb: add static version of system_reset as system_reset2Gravatar Hoàng Đức Hiếu 1-0/+21
generated by cgit v1.2.3 (git 2.46.0) at 2025-08-10 05:46:59 +0000