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2020-04-21More docsmutex_addGravatar Emil Fresk 1-0/+4
2020-04-21Merge branch 'master' into mutex_addGravatar Emil Fresk 24-185/+1119
2020-04-21Update src/mutex.rsGravatar Emil Fresk 1-1/+1
Co-Authored-By: Jonas Schievink <jonasschievink@gmail.com>
2020-04-21UnsafeCell testGravatar Emil Fresk 1-4/+9
2020-04-21Added arch specific mutex implementationGravatar Emil Fresk 3-0/+27
2020-04-15Merge #181Gravatar bors[bot] 7-15/+19
181: Add cfg to Peripheral fields r=thejpster a=hug-dev The cfg conditional compilation attribute was only set on impl blocks of peripherals. This commit also sets it on the fields themselves to be more consistent. Also adds Armv8-M Baseline to the blacklist of the ITM peripheral (cf rule `FMQF` of the Armv8-M ARM). Co-authored-by: Hugues de Valon <hugues.devalon@arm.com>
2020-04-15Merge #180Gravatar bors[bot] 2-1/+277
180: Add Security Attribution Unit support r=thejpster a=hug-dev The SAU is a Armv8-M core peripheral that, alongside the Implementation Defined Attribution Unit, manages the security attribution of the memory zones. This driver provides abstraction to help setting the SAU up. This pull-request adds a new dependency, `bitfield` which provides a really nice way to describe bit fields in registers with methods to access them. It makes it really easier to use/write rather than having to manually declare the shift number and mask constants. Although `bitfield` does not have any dependency, I am well aware of the increased cost of memory its addition could cause to embedded targets. I am really open to criticism about its use, if you would prefer me not to use it, or if you would like to see benchmarks of memory usage for some reference targets of embedded Rust 😃 Co-authored-by: Hugues de Valon <hugues.devalon@arm.com>
2020-04-13Merge #206Gravatar bors[bot] 1-0/+1
206: Add triagebot configuration r=adamgreig a=LeSeulArtichaut This enables [assignment](https://github.com/rust-lang/triagebot/wiki/Assignment) through triagebot on this repository, in preparation for the migration from highfive to triagebot for PR assignment. cc rust-lang/highfive#258 rust-lang/triagebot#433 Co-authored-by: LeSeulArtichaut <leseulartichaut@gmail.com>
2020-04-13Add triagebot configurationGravatar LeSeulArtichaut 1-0/+1
2020-04-10Update cfg gates with Armv8-MGravatar Hugues de Valon 7-15/+19
Update cfg attributes and code documentation to take into consideration the new Armv8-M architecture profiles. Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>
2020-03-18Merge #202Gravatar bors[bot] 1-4/+22
202: Prevent unnecessary bounds check in SCB::{get_priority, set_priority} r=therealprof a=qwerty19106 SystemHandler.index() gives true index for SCB.shpr array. But now it produce unnecessary bounds check. For example, SCB::set_priority: ``` 48: sym.cortex_m::peripheral::scb::__impl_cortex_m::peripheral::SCB_::set_priority::h622cd21bcc3321be (); 0x08000376 push {r7, lr} 0x08000378 mov r7, sp 0x0800037a bl cortex_m::peripheral::scb::SystemHandler::index::hdaf1a31aa5a6a8c5 ; sym.cortex_m::peripheral::scb::SystemHandler::index::hdaf1a31aa5a6a8c5 0x0800037e subs r0, 4 0x08000380 uxtb r0, r0 0x08000382 cmp r0, 0xb ; 11 0x08000384 itttt ls 0x08000386 movw r1, 0xed18 0x0800038a movt r1, 0xe000 0x0800038e movs r2, 0xff 0x08000390 strb r2, [r0, r1] 0x08000392 it ls 0x08000394 pop {r7, pc} 0x08000396 movw r2, 0x1dc0 0x0800039a movs r1, 0xc 0x0800039c movt r2, 0x800 0x080003a0 bl core::panicking::panic_bounds_check::h5181f47ae17a04a5 ; sym.core::panicking::panic_bounds_check::h5181f47ae17a04a5 0x080003a4 trap ``` This PR fix it. Co-authored-by: Роман Кривенков <qwerty19106@gmail.com>
2020-03-18Add TODO with link to rust-lang/rust/issues/13926Gravatar Роман Кривенков 1-0/+4
2020-03-17Update unsafe commentsGravatar Роман Кривенков 1-8/+4
2020-03-17Prevent unnecessary bounds check in SCB::{get_priority, set_priority}Gravatar Роман Кривенков 1-4/+22
2020-03-17Merge #203Gravatar bors[bot] 1-34/+19
203: Use u8 repr for enum instead of custom method r=jonas-schievink a=therealprof This is an alternative proposal to #202 as suggested in https://github.com/rust-embedded/cortex-m/pull/202#issuecomment-600017553 Signed-off-by: Daniel Egger <daniel@eggers-club.de> Co-authored-by: Daniel Egger <daniel@eggers-club.de>
2020-03-17Use u8 repr for enum instead of custom methodGravatar Daniel Egger 1-34/+19
This is an alternative proposal to #202 as suggested in https://github.com/rust-embedded/cortex-m/pull/202#issuecomment-600017553 Signed-off-by: Daniel Egger <daniel@eggers-club.de>
2020-03-15Merge #201Gravatar bors[bot] 9-0/+36
201: Add UDF instruction. Closes #199. r=jonas-schievink a=adamgreig Co-authored-by: Adam Greig <adam@adamgreig.com>
2020-03-15Swap infinite loops for unreachable_unchecked()Gravatar Adam Greig 9-3/+2
2020-03-15Merge #200Gravatar bors[bot] 1-1/+1
200: Add CPSR to asm::delay's clobber flags. Fixes #195 r=therealprof a=adamgreig Co-authored-by: Adam Greig <adam@adamgreig.com>
2020-03-15Mark asm::udf as divergentGravatar Adam Greig 1-3/+8
2020-03-15Add UDF instruction. Closes #199.Gravatar Adam Greig 9-0/+32
2020-03-15Add CPSR to asm::delay's clobber flags. Fixes #195Gravatar Adam Greig 1-1/+1
2020-03-14Merge #189Gravatar bors[bot] 10-3/+421
189: Initial Rust CMSE support r=thejpster a=hug-dev Armv8-M and Armv8.1-M architecture profiles have an optional Security Extension which provides a set of Security features. This patch adds initial support of the Cortex-M Security Extensions but providing support for the TT intrinsics and helper functions on top of it in the newly added `cmse` module of this crate. The code is a Rust idiomatic implementation of the C requirements described in this document: https://developer.arm.com/docs/ecm0359818/latest Executed `assemble.sh` to generate the new static libraries containing the `TT*` instructions. Tested `check_blobs.sh` locally and it passed. Tested on QEMU using the `mps2-an505` machine. Co-authored-by: Hugues de Valon <hugues.devalon@arm.com>
2020-03-14Allow clippy::match_single_bindingGravatar Hugues de Valon 2-0/+4
Clippy complains that the match expressions used for cfg gating could be rewritten as a let statement, this is a false positive. Also adds inline on two functions. Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>
2020-03-02Initial Rust CMSE supportGravatar Hugues de Valon 9-3/+417
Armv8-M and Armv8.1-M architecture profiles have an optional Security Extension which provides a set of Security features. This patch adds initial support of the Cortex-M Security Extensions but providing support for the TT intrinsics and helper functions on top of it in the newly added cmse module of this crate. The code is a Rust idiomatic implementation of the C requirements described in this document: https://developer.arm.com/docs/ecm0359818/latest Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>
2020-03-01Merge #193Gravatar bors[bot] 1-35/+27
193: Make `Peripherals` non-exhaustive and improve its docs r=therealprof a=jonas-schievink This means that it's no longer a breaking change to add fields to it, which is important since Arm is likely to add more in upcoming architectures. They could also add extensions that add peripherals. Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
2020-03-01Merge #198Gravatar bors[bot] 1-2/+2
198: Remove unnecessary parenthesis r=jonas-schievink a=hug-dev Otherwise Cargo complains! This should fix the CI for #193 and #189 Co-authored-by: Hugues de Valon <hugues.devalon@arm.com>
2020-03-01Remove unnecessary parenthesisGravatar Hugues de Valon 1-2/+2
Otherwise Cargo complains! Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>
2020-02-05Merge #192Gravatar bors[bot] 3-94/+298
192: Update and improve cache operations. r=jonas-schievink a=adamgreig Closes #47, #188. I've implemented the proposed methods from #47 and marked all d-cache invalidation functions as unsafe. It's not unsafe to invalidate i-cache or branch predictor as they are read-only caches. The clean and clean+invalidate operations do not alter memory from the executing core's point of view so are also safe. It wasn't possible to remove the requirement to pass in `&mut CPUID` as you require synchronized access to `CPUID` to read the number of sets and ways in the cache, which is required to fully clean or invalidate them, which is required to enable or disable them. So it goes. Breaking change due to changing safety of d-cache invalidation functions. Co-authored-by: Adam Greig <adam@adamgreig.com>
2020-02-04Add missing inline(always) and change more initialised->initializedGravatar Adam Greig 2-8/+9
2020-02-04Apply suggestions from code reviewGravatar Adam Greig 1-28/+28
Co-Authored-By: Jonas Schievink <jonasschievink@gmail.com>
2020-02-04Update documentation for cache functions; use dynamic cache line sizeGravatar Adam Greig 2-49/+124
2020-01-16Use a private field instead of `#[non_exhaustive]`Gravatar Jonas Schievink 1-1/+5
2020-01-16Make `Peripherals` `#[non_exhaustive]`Gravatar Jonas Schievink 1-0/+1
2020-01-16Clean up the doc examples in `peripheral`Gravatar Jonas Schievink 1-35/+22
The Clippy lint was unnecessarily `#[allow]`ed.
2020-01-15Update and improve cache operations.Gravatar Adam Greig 2-72/+200
Closes #47, #188. Breaking change due to changing safety of d-cache invalidation functions.
2020-01-15Merge #191Gravatar bors[bot] 4-88/+4
191: Remove deprecated APIs and the `const-fn` feature r=adamgreig a=jonas-schievink Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
2020-01-15Remove deprecated APIs and the `const-fn` featureGravatar Jonas Schievink 4-88/+4
2020-01-15Merge #190Gravatar bors[bot] 3-50/+64
190: Remove `aligned`, improve ITM code r=adamgreig a=jonas-schievink This does a handful of things: * Removes the dependency on `aligned` (and thus `as-slice` and the 2 versions of `generic-array`), instead providing our own simplified `Aligned` wrapper * Moves the innards of `write_aligned` to its own function, and calls that from `write_all` instead of transmuting `&[u8]` to `&Aligned<A4, [u8]>` (which is likely UB) * Fixes the doc example, which didn't compile anymore * Sinks the `#[allow]` attributes into the functions so they only cover the statements they need to Closes https://github.com/rust-embedded/cortex-m/issues/184 Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
2020-01-15Fix typoGravatar Jonas Schievink 1-1/+1
2020-01-15Remove `aligned`, improve ITM codeGravatar Jonas Schievink 3-50/+64
2020-01-13Merge #187v0.6.2Gravatar bors[bot] 3-2/+10
187: 0.6.2 r=therealprof a=jonas-schievink Closes #185 Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
2020-01-13Uncomment one println in build.rsGravatar Jonas Schievink 1-1/+1
Even though this cfg isn't currently used, printing it doesn't hurt, and it avoids a Clippy lint
2020-01-13Update changelog for 0.6.2Gravatar Jonas Schievink 1-0/+8
2020-01-13Bump version to 0.6.2Gravatar Jonas Schievink 1-1/+1
2019-12-18Add Security Attribution Unit supportGravatar Hugues de Valon 3-1/+278
The SAU is a Armv8-M core peripheral that, alongside the Implementation Defined Attribution Unit, manages the security attribution of the memory zones. This driver provides abstraction to help setting the SAU up. Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>
2019-11-28Merge #175Gravatar bors[bot] 9-0/+31
175: Enable the missing_inline_in_public_items clippy lint. r=jonas-schievink a=m-ou-se This adds `#![deny(clippy::missing_inline_in_public_items)]` to make sure all functions in this crate are marked `#[inline]`, unless they are explicitly marked with `#[allow(clippy::missing_inline_in_public_items)]`. Only three functions in this crate are not `#[inline]`: - `write_words` - `write_all` - `write_aligned` Additionally, the derived `Debug` impl's also have a non-inline implementations. This unfortunately means that the allow attribute also needs to added to any types deriving `Debug`. See also #171 and https://github.com/rust-embedded/cortex-m/pull/174#issuecomment-547304467. Co-authored-by: Mara Bos <m-ou.se@m-ou.se>
2019-11-26Add explanation about clippy::missing_inline_in_public_items lint.Gravatar Mara Bos 1-0/+14
2019-10-29Enable the missing_inline_in_public_items clippy lint.Gravatar Mara Bos 9-0/+17
2019-10-29Merge #171Gravatar bors[bot] 13-0/+103
171: Add `#[inline]` to lots of trivial functions. r=korken89 a=m-ou-se Now the only public non-inline functions left are: - `write_all` - `write_aligned` - All (derived) `Debug` implementations (Checked using Clippy's [`missing_inline_in_public_items`][1] lint.) [1]: https://rust-lang.github.io/rust-clippy/master/#missing_inline_in_public_items Co-authored-by: Mara Bos <m-ou.se@m-ou.se>
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