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467: cortex-m-rt: Remove LR push, to ensure the stack is 8-byte aligned. r=adamgreig a=Dirbaio
This was causing incorrect execution of code optimized with the assumption the stack is 8-byte aligned.
Alternate version of #463
- Remove instead of fix the sentinel/fake frame.
- Remove code initializing LR, since it's now clobbered by the `bl main` anyway.
- ~~Remove the .cfi directives, since Reset now has no correct CFI info. I think this is the "correct" thing to do here.~~
- ~~Initialize the frame pointer in R7 (suggestion from `@jamesmunns)~~`
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
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This was causing incorrect execution of code optimized with the assumption the stack is 8-byte aligned.
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465: Enforce 8-byte initial stack pointer alignment r=adamgreig a=adamgreig
After #463 we discovered that adding a second linker script via another compiler flag could be used to override `_stack_start` without triggering the assert in the main linker script. By masking the value, we force alignment even when the assert doesn't otherwise trigger.
Co-authored-by: Adam Greig <adam@adamgreig.com>
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464: cortex-m-rt: assert in linker script that stack_start is 8-byte aligned. r=adamgreig a=Dirbaio
If the user sets RAM length to something that's not multiple of 8, the stack won't be 8-byte aligned. This'll trigger the same horrible symptoms as #463 .
This PR adds an assert to the linker script that enforces alignment.
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
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462: panic-itm: update crate config so docs aren't empty r=newAM a=tgross35
The docs are currently empty since the module is disabled https://docs.rs/panic-itm/0.4.2/panic_itm/index.html
Co-authored-by: Trevor Gross <tmgross@umich.edu>
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422: Add ITNS field to NVIC peripheral r=adamgreig a=sphw
This PR adds the ITNS (Interrupt Target Non-secure) field to the NIVC peripheral. This field is required to write a boot loader for TrustZone-M devices, since it allows the user to use interrupts from non-secure states.
I believe I have maintained the correct padding for the next fields, but I have not tested these changes on a non M33 device. So a close review and test would be appreciated.
Co-authored-by: Sascha Wise <me@saschawise.com>
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454: Prepare for cortex-m-rt 0.7.2 r=therealprof a=adamgreig
It's been about a year since the last release so may as well get the couple of bug fixes and new assembly out, I think. This also adds the new set-vtor and set-sp features.
Co-authored-by: Adam Greig <adam@adamgreig.com>
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451: Small critical-section-related fixes. r=adamgreig a=Dirbaio
See individual commit messages.
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
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This avoids having to do `#[doc(hidden)] pub mod critical_section` which is a bit strange.
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447: Add implementation for critical-section 1.0 r=adamgreig a=Dirbaio
Picking up #433 since it seems stalled. Changes from #433 are:
- Update to `critical-section 1.0.0-alpha.2`
- Use `bool` restore token
- Name Cargo feature `critical-section-single-core`.
TODO before merging:
- [x] Wait for `critical-section 1.0` release https://github.com/rust-embedded/critical-section/pull/19
Co-Authored-By: Markus Reiter `@reitermarkus`
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
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450: Fix CI compiletest breakage due to Rust 1.63 r=adamgreig a=Dirbaio
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
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Co-Authored-By: Markus Reiter <me@reitermark.us>
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439: fix bug on cmse::TestTarget::mpu_region r=thejpster a=luojia65
This function should read `mrvalid` and `mregion` fields from test target result, instead of `srvalid` and `sregion`.
Co-authored-by: Luo Jia <me@luojia.cc>
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440: Fix typos in cortex-m-rt lib.rs r=newAM a=danbev
Co-authored-by: Daniel Bevenius <daniel.bevenius@gmail.com>
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This function should read `mrvalid` and `mregion` fields from test target result, instead of `srvalid` and `sregion`.
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435: ci: update github-actions r=adamgreig a=newAM
* actions/checkout 2 -> 3
* actions/download-artifact 2 -> 3
* actions/upload-artifact 2 -> 3
* imjonbo/issue-bot 2 -> 3
This fixes on-target CI. The self-hosted runner updated and removed node v12, because it is EOL and no longer receiving security updates.
* `actions` changes do not break anything, they just update node.
* `issue-bot` has breaking changes, but I do not think they apply: [release notes](https://github.com/imjohnbo/issue-bot/releases/tag/v3.0.0)
Co-authored-by: Alex Martens <alex@thinglab.org>
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* actions/checkout 2 -> 3
* actions/download-artifact 2 -> 3
* actions/upload-artifact 2 -> 3
* imjonbo/issue-bot 2 -> 3
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434: rt: fix veneer limit position in linker script r=adamgreig a=luojia65
This pull request fixes a CMSE related bug. If we define `#[cmse_nonsecure_call]` segments it would generate functions in `.gnu.sgstubs`, but we would eventually found out that for unknown reason `__veneer_base` == `__veneer_limit`, where SAU configuration to this segment would be impossible.
The reason for this bug is unknown, but after this pull request it would link into correct limit value.
I wrote an example for this fix: https://github.com/IoTS-P/trustzone-m-rs/tree/sgstub-fixed . Before this pull request, this project builds but it would print like `SG function stub region is at 0x10005fc0 .. 0x10005fc0`, resulting in secure fault. After this pull request, it would print `SG function stub region is at 0x10005fc0 .. 0x10005fe0` and runs successfully.
Co-authored-by: luojia65 <me@luojia.cc>
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add description and hints on linker behavior at symbol `__veneer_limit`
Co-authored-by: Adam Greig <adam@adamgreig.com>
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432: Fix inline assembly. r=adamgreig a=reitermarkus
Fix some differences between previous `asm.S` and inline assembly.
Co-authored-by: Markus Reiter <me@reitermark.us>
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429: Exclude testsuite from cron, fixes #427 r=therealprof a=adamgreig
Turns out #427 was caused by #355 after all, because the CI workflow was updated to exclude testsuite from its default `cargo test`, but the cron workflow wasn't.
For now this seems like the simplest fix; eventually it might be nice to have cron run the testsuite too (at least in qemu), but really cron's there to catch surprise compilation failures when new Rust versions or new dependency releases come out, so I don't think it's urgent.
Co-authored-by: Adam Greig <adam@adamgreig.com>
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355: Add on-target tests to CI r=thejpster a=newAM
A week ago in the rust-embedded matrix chat `@adamgreig` mentioned that on-target CI would be helpful for the `cortex-m` and `cortex-m-rt` crates. This is a pull-request to make that happen.
## History: Bootstrapping and `cortex-m-rt`
The first problem I came across was the amount of boilerplate required to build an on-target binary without `cortex-m-rt`.
There are two paths forward here:
1. Introduce a lot of boilerplate in `cortex-m`, which will largely be copy-pasted from `cortex-m-rt`.
2. Relocate `cortex-m-rt` to this workspace.
In (#391) `cortex-m-rt` was relocated to this workspace to fix the bootstrapping problem.
## Test Execution
Tests run with QEMU and physical hardware.
QEMU uses the LM3S6965 Cortex-M3 target because it is widely used.
The physical hardware is a NUCLEO-F070RB connected to a self-hosted runner. In the future more hardware can be added to cover more CPUs.
Due to reliability concerns with self-hosted runners only QEMU will be a required status check in CI, the physical hardware checks will be informational only.
### CI Software
The CI software for running on physical hardware is simply a self-hosted github actions runner. A working demonstration of this can be found [here](https://github.com/newAM/totally-not-a-cortex-m-fork/runs/5345451343?check_suite_focus=true) (the repository does not appear as a fork to work around github actions limitations with forks).
The runner uses [`probe-run`] to execute the tests on embedded hardware. [`probe-run`] was chosen for several reasons:
* Actively maintained by [knurling-rs], with an actively maintained back-end from [`probe-rs`].
* Written in rust. Understanding the code does not require contributors to learn a new language.
* Designed with on-target testing as a primary goal (for use with [`defmt-test`]).
* Automatic unwinding and backtrace display.
## Test Harness
This PR introduces a test harness, `minitest`.
`minitest` is almost identical to [`defmt-test`], the only difference is that it replaces [`defmt`] with [`rtt-target`] because [`defmt`] introduces a dependency cycle on `cortex-m`.
This is harness is very minimal, adding only 327 lines of rust:
```console
$ tokei testsuite/minitest
===============================================================================
Language Files Lines Code Comments Blanks
===============================================================================
Markdown 1 7 0 4 3
TOML 2 41 34 0 7
-------------------------------------------------------------------------------
Rust 3 406 350 5 51
|- Markdown 1 8 0 7 1
(Total) 414 350 12 52
===============================================================================
Total 6 454 384 9 61
===============================================================================
```
The test harness does introduce some abstraction, and may not be suitable for all tests. Lower-level tests are still possible without the harness using `asm::udf` to fail the test, and `asm::bkpt` to exit without failure.
## Reliability and Uptime
I have been doing automatic on-target testing for the [`stm32wlxx-hal`] using [`probe-run`]. Over hundreds of automatic runs spanning several months I have had no failures as a result of external factors (USB connectivity, programming errors, ect.). I do not anticipate on-target CI being perfect, but at the same time I do not anticipate frequent problems.
[`defmt-test`]: https://github.com/knurling-rs/defmt/tree/main/firmware/defmt-test
[`defmt`]: https://ferrous-systems.com/blog/defmt/
[`probe-rs`]: https://probe.rs/
[`probe-run`]: https://github.com/knurling-rs/probe-run
[`rtt-target`]: https://crates.io/crates/rtt-target
[`stm32wlxx-hal`]: https://github.com/stm32-rs/stm32wlxx-hal
[knurling-rs]: https://knurling.ferrous-systems.com/
Co-authored-by: Alex Martens <alex@thinglab.org>
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424: Prepare for c-m-sh v0.4.2, p-sh v0.6.0 r=newAM a=adamgreig
This PR prepares for a release of cortex-m-semihosting 0.4.2 and panic-semihosting 0.6.0. Since we never had a non-yanked 0.4.x version of cortex-m-semihosting, this is essentially a new breaking release for both crates. The main change is the use of the new asm macro, with the removal of the inline-asm feature and bumped MSRV.
Co-authored-by: Adam Greig <adam@adamgreig.com>
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425: Remove prelude. r=therealprof a=Dirbaio
Hoping to sneak this in before 0.8 :)
The prelude just reexports all of `embedded-hal 0.2`'s prelude. With EH1.0 around the corner it would be a shame to get stuck with 0.2 in the prelude, and changing it later is a breaking change.
Also, EH1.0 has removed the prelude.
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
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423: Swap to just-stabilised asm!() and global_asm!() macros r=thejpster a=adamgreig
Once Rust 1.59 is released in a couple of days, the `asm!()` and `global_asm!()` macros will become stable, and we will no longer require the various precompiled binaries we've used until now in cortex-m and cortex-m-rt. cc #420.
This PR uses `asm!()` in cortex-m, and removes the inline-asm feature, since I anticipate this going into cortex-m 0.8 and so we don't need to leave it behind for compatibility. In various places the previous version would call an extern C method when built for the native target, which would only fail at link time; to preserve the ability to build on x86 I've either made the whole method require the `cortex_m` configuration, or where appropriate/convenient simply skipped the `asm!()` call.
This PR replaces the old gcc-preprocessed `asm.S` in cortex-m-rt with use of `global_asm!()`, although since you can't normally use `#[cfg(...)]` attributes with `global_asm!()`, there's also a slightly scary macro modified from one invented by `@Dirbaio` for a similar purpose. I considered putting the initialisation of LR behind an armv6m flag, but since we want to restore it after calling `__pre_init` it seemed better to just leave it the same on both targets. I added Cargo features to optionally set SP and VTOR at startup, which has been variously requested but would previously have required multiplicatively more pre-built binaries. Now: no problem. Relevant issues:
* https://github.com/rust-embedded/cortex-m-rt/issues/283
* https://github.com/rust-embedded/cortex-m-rt/issues/55
* https://github.com/rust-embedded/cortex-m-rt/issues/254
* https://github.com/rust-embedded/cortex-m-rt/issues/102
* https://github.com/rust-embedded/cortex-m-rt/pull/338
I've tested these on a couple of targets (and updated the CI): on the whole there's a small improvement in code size due to everyone getting inlined asm, especially in `cortex_m::interrupt::free()`.
The major downside is we bump our MSRV from 1.42 (March 2020) to 1.59 (Feb 2022). For cortex-m, I propose putting these changes in the upcoming 0.8 release (which is technically what the master branch is already on) and not backporting. For cortex-m-rt I'm not sure: we don't have any other pending breaking changes, so we could consider a patch release. Anyway, this PR doesn't commit to any particular releases, so we can decide that later.
For cortex-m-semihosting/panic-semihosting I think a patch release would be ideal, especially since we had to yank the last c-m-sh release due to conflicting prebuilt binaries (a problem that should now vanish).
Also tagging these issues that I think might also benefit from new inline asm:
* https://github.com/rust-embedded/cortex-m/issues/265
* https://github.com/rust-embedded/cortex-m/issues/215
* https://github.com/rust-embedded/cortex-m/issues/406
Co-authored-by: Adam Greig <adam@adamgreig.com>
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depend on cortex-m 0.8
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entirely
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add inline to most cortex_m::asm methods
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checking code that uses it on native platform.
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Adam Greig
bors[bot]
Dario Nieuwenhuis
Trevor Gross
Sascha Wise
Daniel Bevenius
Luo Jia
Alex Martens
Markus Reiter
