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2021-02-19Remove an extra function call in `primask::read`Gravatar yvt 1-5/+1
There doesn't seem to be any reason why the call to `__primask_r` should be wrapped by another function call.
2021-01-07Merge #313Gravatar bors[bot] 9-17/+0
313: Remove excessive #[allow(clippy::missing_inline_in_public_items)] r=adamgreig a=jonas-schievink Closes https://github.com/rust-embedded/cortex-m/issues/179 Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
2021-01-07Remove excessive missing_inline_in_public_itemsGravatar Jonas Schievink 9-17/+0
2021-01-07Fix timing of asm-based delay implementationGravatar Jonas Schievink 1-5/+3
2020-12-03Update msp::write deprecation messageGravatar Jonas Schievink 1-1/+1
2020-12-02Deprecate msp::writeGravatar Jonas Schievink 1-0/+1
2020-12-02Update src/asm.rsGravatar Adam Greig 1-1/+1
Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
2020-12-02asm.bootstrap: only set CONTROL.SPSEL, mark as divergentGravatar Adam Greig 1-10/+14
2020-12-02Expose __syscall and add new bootstrap methodGravatar Adam Greig 1-0/+41
2020-11-10Remove useless deprecation warning on InterruptNumber ifor NrGravatar Adam Greig 1-4/+0
2020-10-26Add missing #[inline]Gravatar Jonas Schievink 1-0/+1
2020-10-26Format everythingGravatar Jonas Schievink 5-11/+25
2020-10-02Add some Armv8-M assembly routinesGravatar Hugues de Valon 2-0/+28
Adds access to MSP_NS and the BXNS instruction. Also adds __dsb which was missing. Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>
2020-09-20Implement InterruptNumber for bare_metal::NrGravatar Adam Greig 1-1/+10
2020-08-31Update documented MSRVGravatar Jonas Schievink 1-1/+1
2020-08-29Merge asm implementationsGravatar Jonas Schievink 18-752/+120
2020-08-27Merge #259Gravatar bors[bot] 1-0/+26
259: Rust assembly stubs r=thalesfragoso a=jonas-schievink Disclaimer: I have not tested any of this (help wanted, we have no tests in here). Thanks to @therealprof for nerd-sniping me into oblivion. Fixes https://github.com/rust-embedded/cortex-m/issues/254 Fixes https://github.com/rust-embedded/cortex-m/issues/194 Fixes https://github.com/rust-embedded/cortex-m/issues/139 # Summary * Remove the assembly files in favor of a new `asm.rs`, which uses unstable inline assembly and provides a C ABI interface. * Replace the shell scripts by a [`cargo-xtask`](https://github.com/matklad/cargo-xtask/). * While we're at it, also pre-build artifacts that are compatible with linker-plugin LTO, fixing https://github.com/rust-embedded/cortex-m/issues/139 (again, not tested) This means that contributors and maintainers just need ~~a nightly Rust compiler installed~~ to run `cargo xtask assemble`. No binutils, no assembler, no `ar`, no GCC/Clang, and especially nothing from the godawful Arm servers, fixing https://github.com/rust-embedded/cortex-m/issues/194. You don't even have to install the correct nightly Rust toolchain, `cargo xtask` does it for you (and installs all the thumb targets too). Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
2020-08-27Remove outdated TODOGravatar Jonas Schievink 2-3/+3
2020-08-27Move feature docs to lib.rs and improve themGravatar Jonas Schievink 1-0/+26
2020-08-25Moar full stops.Gravatar Vadim Kaushan 1-4/+4
2020-08-24Add preludeGravatar Vadim Kaushan 2-0/+4
2020-08-24Update src/delay.rsGravatar Vadim Kaushan 1-1/+1
Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
2020-08-23Provide a delay driver based on SysTickGravatar Vadim Kaushan 2-0/+120
2020-07-27Peipheral deref/ptr APIs now use associated const PTRGravatar JOE1994 1-30/+30
2020-07-27rename associated consts to 'PTR'Gravatar JOE1994 1-14/+14
2020-07-27add ptr to registerblock as associated constantGravatar JOE1994 1-14/+56
This commit introduces new associated constants to Core Peripherals. (pointers to the register block) This commit also adds a notice that 'ptr()' APIs will be deprecated in v0.7.
2020-07-27make 'fn ptr()' APIs to be 'const fn ptr()'Gravatar JOE1994 1-15/+15
2020-07-22Merge #241Gravatar bors[bot] 2-34/+53
241: Add new InterruptNumber trait r=therealprof a=adamgreig This is a first go at the new trait needed for https://github.com/rust-embedded/svd2rust/pull/455 since we removed `Nr` from bare-metal. In this case I've written it as `unsafe trait InterruptNumber: Into<u16>` rather than providing a conversion method inside the trait; I think this is neat and idiomatic but please correct me if there's a reason to not do it like this. [Here's](https://play.rust-lang.org/?version=stable&mode=debug&edition=2018&gist=4f2f8b9604b5a62298f9907780d844c7) a playground link showing an example implementation. Co-authored-by: Adam Greig <adam@adamgreig.com>
2020-07-21please clippyGravatar Thales Fragoso 1-2/+2
2020-07-21Remove unused import in thumbv6Gravatar Thales Fragoso 1-1/+3
2020-07-21Add new InterruptNumber traitGravatar Adam Greig 2-34/+53
2020-07-18Correct typo in RASR register aliasesGravatar R. Kyle Murphy 2-9/+9
Fixes the typo in the a1, a2, and a3 aliases of the RASR MPU register.
2020-07-12Allow the taken flag to be optimized outGravatar Jonas Schievink 1-3/+6
2020-07-09Expand iff and reword last sentenceGravatar Daniel Egger 1-2/+2
Signed-off-by: Daniel Egger <daniel@eggers-club.de>
2020-07-09Change spelling of initialisation to AEGravatar Daniel Egger 1-1/+1
Signed-off-by: Daniel Egger <daniel@eggers-club.de>
2020-07-09Update src/asm.rsGravatar Daniel Egger 1-1/+1
Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
2020-07-09Better delay descriptionGravatar Daniel Egger 1-4/+7
CC #236 Signed-off-by: Daniel Egger <daniel@eggers-club.de>
2020-07-05Merge pull request #205 from hug-dev/enable-exceptionsGravatar Daniel Egger 1-0/+75
Add SCB methods to enable/disable exceptions
2020-07-05Use assembly sequences to enable caches.Gravatar Cliff L. Biffle 1-8/+16
See #232, which this partially fixes -- there's still the question of taking an interrupt in the midst of these sequences.
2020-06-24Add a function to get SHCSR enable bit positionsGravatar Hugues de Valon 1-47/+28
This removes the duplication of the look-up table and enforces some safety checks with the match statement. Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>
2020-06-19Correct the documentation for the `SCB::set_pendst` functionGravatar Peter Taylor 1-1/+1
2020-06-11Merge #220Gravatar bors[bot] 2-0/+350
220: Implement accessing FPSCR r=adamgreig a=bugadani On the nRF52, sometimes it is necessary to manipulate the FPSCR register, otherwise the device wakes up immediately from sleep. (At least on this device) the FPSCR is only available through `vmrs` instructions. I've implemented reading the register, parsing its bits and writing a raw value to the register, but let me know if I should also implement manipulation of the named bits. I would also like to request some assistance to get this to actually build, it's not clear to me how `.s` files are compiled in this library. I'm also not certain where the actual place for this would be - in the registers, or in the `fpu` module. Co-authored-by: Dániel Buga <bugadani@gmail.com> Co-authored-by: Dániel Buga <daniel@revolutionrobotics.org>
2020-06-10Merge #225 #226Gravatar bors[bot] 3-2/+113
225: Initial ARMv8-M MPU support. r=adamgreig a=cbiffle The v8-M MPU is entirely different from, and incompatible with, the earlier PMSA MPU. And so this commit does two things: 1. Makes the old RegisterBlock depend on armv6m (for M0+) and armv7m. 2. Defines a new RegisterBlock containing the right layout for v8m. The hack for documenting fields by opting in x86-64 means the v8m version won't appear in the docs. 226: Expose the orphaned ICTR/ACTLR registers. r=adamgreig a=cbiffle In ARMv7-M these were floating alone in system control space, without a unifying name. As a result, they weren't exposed in earlier versions of this crate. In ARMv8-M they have been given a name, the Implementation Control Block, and more registers have been added. I've used that name for all architecture revisions. Co-authored-by: Cliff L. Biffle <cliff@oxide.computer>
2020-06-10Merge #227Gravatar bors[bot] 1-1/+12
227: ITM: don't test reserved bits in is_fifo_ready r=adamgreig a=bcantrill This is a follow up to the discussion in #219, capturing the conclusion by @cbiffle and @adamgreig there: to indicate that the ITM FIFO is ready on FIFOREADY (only) on ARMv7-M (only) and to indicate the FIFI is ready on *either* FIFOREADY *or* DISABLED on ARMv8-M. ITM has been tested and verified on an ARMv7-M CPU (an STM32F407, a Cortex-M4) and an ARMv8-M CPU (an LPC55S69, a Cortex-M33). Without this fix, any use of ITM will hang on ARMv8-M -- which may in fact be the root cause of #74... Co-authored-by: Cliff L. Biffle <cliff@oxide.computer>
2020-06-09ITM: don't test reserved bits in is_fifo_readyGravatar Cliff L. Biffle 1-1/+12
On ARMv7-M, bits 31:1 of the value read from STIMx are reserved, so comparing them against zero is a bad idea. On ARMv8-M, bit 1 has been repurposed to indicate DISABLED. This means that the is_fifo_ready impl hangs forever when ITM is disabled on a Cortex-M33 (for example). Changed to test only the FIFOREADY bit on ARMv7-M, and to test either FIFOREADY or DISABLED on ARMv8-M.
2020-06-09Expose the orphaned ICTR/ACTLR registers.Gravatar Cliff L. Biffle 2-1/+77
In ARMv7-M these were floating alone in system control space, without a unifying name. As a result, they weren't exposed in earlier versions of this crate. In ARMv8-M they have been given a name, the Implementation Control Block, and more registers have been added. I've used that name for all architecture revisions.
2020-06-09Initial ARMv8-M MPU support.Gravatar Cliff L. Biffle 1-1/+36
The v8-M MPU is entirely different from, and incompatible with, the earlier PMSA MPU. And so this commit does two things: 1. Makes the old RegisterBlock depend on armv6m (for M0+) and armv7m. 2. Defines a new RegisterBlock containing the right layout for v8m. The hack for documenting fields by opting in x86-64 means the v8m version won't appear in the docs.
2020-06-06Add #[allow(clippy::missing_inline_in_public_items)] for consistencyGravatar Dániel Buga 1-0/+1
2020-06-06Make RMode methods actually accessibleGravatar Dániel Buga 1-4/+4
2020-06-06Add missing #[inline]sGravatar Dániel Buga 1-0/+14
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