From ebf2dd6a3414a755b7f93dfea26dc30db31a842a Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Tue, 14 Feb 2023 01:51:03 +0100 Subject: cortex-m-rt: Remove LR push, to ensure the stack is 8-byte aligned. This was causing incorrect execution of code optimized with the assumption the stack is 8-byte aligned. --- cortex-m-rt/src/lib.rs | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git a/cortex-m-rt/src/lib.rs b/cortex-m-rt/src/lib.rs index 6f72197..2070efa 100644 --- a/cortex-m-rt/src/lib.rs +++ b/cortex-m-rt/src/lib.rs @@ -507,12 +507,6 @@ cfg_global_asm! { ".cfi_startproc Reset:", - // Ensure LR is loaded with 0xFFFF_FFFF at startup to help debuggers find the first call frame. - // On ARMv6-M LR is not initialised at all, while other platforms should initialise it. - "movs r4, #0 - mvns r4, r4 - mov lr, r4", - // If enabled, initialise the SP. This is normally initialised by the CPU itself or by a // bootloader, but some debuggers fail to set it when resetting the target, leading to // stack corruptions. @@ -533,9 +527,7 @@ cfg_global_asm! { // Run user pre-init code which must be executed immediately after startup, before the // potentially time-consuming memory initialisation takes place. // Example use cases include disabling default watchdogs or enabling RAM. - // Reload LR after returning from pre-init (r4 is preserved by subroutines). - "bl __pre_init - mov lr, r4", + "bl __pre_init", // Initialise .bss memory. `__sbss` and `__ebss` come from the linker script. "ldr r0, =__sbss @@ -572,12 +564,6 @@ cfg_global_asm! { dsb isb", - // Push `lr` to the stack for debuggers, to prevent them unwinding past Reset. - // See https://sourceware.org/binutils/docs/as/CFI-directives.html. - ".cfi_def_cfa sp, 0 - push {{lr}} - .cfi_offset lr, 0", - // Jump to user main function. // `bl` is used for the extended range, but the user main function should not return, // so trap on any unexpected return. -- cgit v1.2.3