From 9b51b40a96f94a144b6f2006729ac01c52896c67 Mon Sep 17 00:00:00 2001 From: Adam Greig Date: Fri, 17 Feb 2023 21:22:49 +0000 Subject: Move zero-init-ram to just before bss initialisation, so that pre_init occurs before --- cortex-m-rt/src/lib.rs | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) (limited to 'cortex-m-rt/src') diff --git a/cortex-m-rt/src/lib.rs b/cortex-m-rt/src/lib.rs index 30fe37e..a6d946c 100644 --- a/cortex-m-rt/src/lib.rs +++ b/cortex-m-rt/src/lib.rs @@ -521,19 +521,6 @@ cfg_global_asm! { "ldr r0, =_stack_start msr msp, r0", - // If enabled, initialize RAM with zeros. This is not usually required, but might be necessary - // to properly initialize checksum-based memory integrity measures on safety-critical hardware. - #[cfg(feature = "zero-init-ram")] - "ldr r0, =_ram_start - ldr r1, =_ram_end - movs r2, #0 - 0: - cmp r1, r0 - beq 1f - stm r0!, {{r2}} - b 0b - 1:", - // If enabled, initialise VTOR to the start of the vector table. This is normally initialised // by a bootloader when the non-reset value is required, but some bootloaders do not set it, // leading to frustrating issues where everything seems to work but interrupts are never @@ -549,6 +536,19 @@ cfg_global_asm! { // Example use cases include disabling default watchdogs or enabling RAM. "bl __pre_init", + // If enabled, initialize RAM with zeros. This is not usually required, but might be necessary + // to properly initialize checksum-based memory integrity measures on safety-critical hardware. + #[cfg(feature = "zero-init-ram")] + "ldr r0, =_ram_start + ldr r1, =_ram_end + movs r2, #0 + 0: + cmp r1, r0 + beq 1f + stm r0!, {{r2}} + b 0b + 1:", + // Initialise .bss memory. `__sbss` and `__ebss` come from the linker script. #[cfg(not(feature = "zero-init-ram"))] "ldr r0, =__sbss -- cgit v1.2.3