From ac7eaef31a01258a90aa786bbce4d47b17e207c6 Mon Sep 17 00:00:00 2001
From: Adam Greig <adam@adamgreig.com>
Date: Mon, 29 Jul 2019 13:52:29 -0600
Subject: Update for 2018 edition

---
 src/peripheral/cpuid.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/peripheral/cpuid.rs')

diff --git a/src/peripheral/cpuid.rs b/src/peripheral/cpuid.rs
index c79ad18..7b86ddc 100644
--- a/src/peripheral/cpuid.rs
+++ b/src/peripheral/cpuid.rs
@@ -5,7 +5,7 @@ use volatile_register::RO;
 use volatile_register::RW;
 
 #[cfg(not(armv6m))]
-use peripheral::CPUID;
+use crate::peripheral::CPUID;
 
 /// Register block
 #[repr(C)]
@@ -104,7 +104,7 @@ impl CPUID {
         const CCSIDR_ASSOCIATIVITY_MASK: u32 = 0x3FF << CCSIDR_ASSOCIATIVITY_POS;
 
         self.select_cache(level, ind);
-        ::asm::dsb();
+        crate::asm::dsb();
         let ccsidr = self.ccsidr.read();
         (
             (1 + ((ccsidr & CCSIDR_NUMSETS_MASK) >> CCSIDR_NUMSETS_POS)) as u16,
-- 
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