From 05ddb442301e617352aba697a2f9927ffc50411c Mon Sep 17 00:00:00 2001 From: Sascha Wise Date: Tue, 15 Feb 2022 19:11:50 -0800 Subject: add itns field to NVIC perph --- src/peripheral/nvic.rs | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/peripheral/nvic.rs b/src/peripheral/nvic.rs index 57fa94b..bd4a045 100644 --- a/src/peripheral/nvic.rs +++ b/src/peripheral/nvic.rs @@ -33,9 +33,16 @@ pub struct RegisterBlock { /// Interrupt Active Bit (not present on Cortex-M0 variants) #[cfg(not(armv6m))] pub iabr: [RO; 16], - #[cfg(armv6m)] + #[cfg(any(armv6m, armv8m))] _reserved4: [u32; 16], + #[cfg(armv8m)] + /// Interrupt Target Non-secure (only present on Arm v8-M) + pub itns: [RW; 16], + #[cfg(armv8m)] + _reserved5: [u32; 32], + + #[cfg(not(armv8m))] _reserved5: [u32; 48], /// Interrupt Priority -- cgit v1.2.3 From 9bff0c8783a1ea6f3ff7aebac1a55fda15968e40 Mon Sep 17 00:00:00 2001 From: Sascha Wise Date: Tue, 15 Mar 2022 08:50:08 -0700 Subject: fix and cleanup offsets in nvic --- src/peripheral/nvic.rs | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/peripheral/nvic.rs b/src/peripheral/nvic.rs index bd4a045..067c1d9 100644 --- a/src/peripheral/nvic.rs +++ b/src/peripheral/nvic.rs @@ -33,17 +33,18 @@ pub struct RegisterBlock { /// Interrupt Active Bit (not present on Cortex-M0 variants) #[cfg(not(armv6m))] pub iabr: [RO; 16], - #[cfg(any(armv6m, armv8m))] + #[cfg(armv6m)] _reserved4: [u32; 16], + _reserved5: [u32; 16], + #[cfg(armv8m)] /// Interrupt Target Non-secure (only present on Arm v8-M) pub itns: [RW; 16], - #[cfg(armv8m)] - _reserved5: [u32; 32], - #[cfg(not(armv8m))] - _reserved5: [u32; 48], + _reserved6: [u32; 16], + + _reserved7: [u32; 16], /// Interrupt Priority /// @@ -74,7 +75,7 @@ pub struct RegisterBlock { pub ipr: [RW; 8], #[cfg(not(armv6m))] - _reserved6: [u32; 580], + _reserved8: [u32; 580], /// Software Trigger Interrupt #[cfg(not(armv6m))] -- cgit v1.2.3