From 1c198a1f53b0fdef53c723843331a059da6cb6a3 Mon Sep 17 00:00:00 2001
From: "Cliff L. Biffle" <cliff@oxide.computer>
Date: Tue, 9 Jun 2020 14:44:59 -0700
Subject: Initial ARMv8-M MPU support.

The v8-M MPU is entirely different from, and incompatible with, the
earlier PMSA MPU. And so this commit does two things:

1. Makes the old RegisterBlock depend on armv6m (for M0+) and armv7m.

2. Defines a new RegisterBlock containing the right layout for v8m.

The hack for documenting fields by opting in x86-64 means the v8m
version won't appear in the docs.
---
 src/peripheral/mpu.rs | 37 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 36 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/peripheral/mpu.rs b/src/peripheral/mpu.rs
index 09d06f0..4d53eb5 100644
--- a/src/peripheral/mpu.rs
+++ b/src/peripheral/mpu.rs
@@ -2,7 +2,8 @@
 
 use volatile_register::{RO, RW};
 
-/// Register block
+/// Register block for ARMv7-M
+#[cfg(any(armv6m, armv7m, target_arch = "x86_64"))] // x86-64 is for rustdoc
 #[repr(C)]
 pub struct RegisterBlock {
     /// Type
@@ -28,3 +29,37 @@ pub struct RegisterBlock {
     /// Alias 3 of RSAR
     pub rsar_a3: RW<u32>,
 }
+
+/// Register block for ARMv8-M
+#[cfg(armv8m)]
+#[repr(C)]
+pub struct RegisterBlock {
+    /// Type
+    pub _type: RO<u32>,
+    /// Control
+    pub ctrl: RW<u32>,
+    /// Region Number
+    pub rnr: RW<u32>,
+    /// Region Base Address
+    pub rbar: RW<u32>,
+    /// Region Limit Address
+    pub rlar: RW<u32>,
+    /// Alias 1 of RBAR
+    pub rbar_a1: RW<u32>,
+    /// Alias 1 of RLAR
+    pub rlar_a1: RW<u32>,
+    /// Alias 2 of RBAR
+    pub rbar_a2: RW<u32>,
+    /// Alias 2 of RLAR
+    pub rlar_a2: RW<u32>,
+    /// Alias 3 of RBAR
+    pub rbar_a3: RW<u32>,
+    /// Alias 3 of RLAR
+    pub rlar_a3: RW<u32>,
+
+    // Reserved word at offset 0xBC
+    _reserved: u32,
+
+    /// Memory Attribute Indirection register 0 and 1
+    pub mair: [RW<u32>; 2],
+}
-- 
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