From 653a4407cb221fbbc8bb06c518fd599d18f90111 Mon Sep 17 00:00:00 2001
From: Dániel Buga <bugadani@gmail.com>
Date: Wed, 27 May 2020 11:45:05 +0200
Subject: Implement accessing FPSCR

---
 src/register/fpscr.rs | 152 ++++++++++++++++++++++++++++++++++++++++++++++++++
 src/register/mod.rs   |   7 +++
 2 files changed, 159 insertions(+)
 create mode 100644 src/register/fpscr.rs

(limited to 'src')

diff --git a/src/register/fpscr.rs b/src/register/fpscr.rs
new file mode 100644
index 0000000..22f6ce1
--- /dev/null
+++ b/src/register/fpscr.rs
@@ -0,0 +1,152 @@
+//! Floating-point Status Control Register
+
+#[allow(clippy::missing_inline_in_public_items)]
+#[derive(Clone, Copy, Debug)]
+pub struct Fpscr {
+    bits: u32,
+}
+
+#[derive(Clone, Copy, Debug)]
+pub enum RMode {
+    Nearest,
+    PlusInfinity,
+    MinusInfinity,
+    Zero,
+}
+
+impl Fpscr {
+    /// Returns the contents of the register as raw bits
+    #[inline]
+    pub fn bits(self) -> u32 {
+        self.bits
+    }
+
+    //! Read the Negative condition code flag
+    #[inline]
+    pub fn n(self) -> bool {
+        self.bits & (1 << 31) != 0
+    }
+
+    //! Read the Zero condition code flag
+    #[inline]
+    pub fn z(self) -> bool {
+        self.bits & (1 << 30) != 0
+    }
+
+    //! Read the Carry condition code flag
+    #[inline]
+    pub fn c(self) -> bool {
+        self.bits & (1 << 29) != 0
+    }
+
+    //! Read the Overflow condition code flag
+    #[inline]
+    pub fn v(self) -> bool {
+        self.bits & (1 << 28) != 0
+    }
+
+    #[inline]
+    pub fn ahp(self) -> bool {
+        if self.bits & (1 << 26) != 0
+    }
+
+    #[inline]
+    pub fn dn(self) -> bool {
+        if self.bits & (1 << 25) != 0
+    }
+
+    #[inline]
+    pub fn fz(self) -> bool {
+        if self.bits & (1 << 24) != 0
+    }
+
+    #[inline]
+    pub fn rmode(self) -> RMode {
+        match self.bits & (3 << 22) {
+            0 << 22 => RMode::Nearest,
+            1 << 22 => RMode::PlusInfinity,
+            2 << 22 => RMode::MinusInfinity,
+            3 << 22 => RMode::Zero,
+        }
+    }
+
+    #[inline]
+    pub fn idc(self) -> bool {
+        if self.bits & (1 << 7) != 0
+    }
+
+    #[inline]
+    pub fn ixc(self) -> bool {
+        if self.bits & (1 << 4) != 0
+    }
+
+    #[inline]
+    pub fn ufc(self) -> bool {
+        if self.bits & (1 << 3) != 0
+    }
+
+    #[inline]
+    pub fn ofc(self) -> bool {
+        if self.bits & (1 << 2) != 0
+    }
+
+    #[inline]
+    pub fn dzc(self) -> bool {
+        if self.bits & (1 << 1) != 0
+    }
+
+    #[inline]
+    pub fn ioc(self) -> bool {
+        if self.bits & (1 << 0) != 0
+    }
+}
+
+/// Read the FPSCR register
+pub fn read() -> Fpscr {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => {
+            let r: u32;
+            unsafe {
+                llvm_asm!("vmrs $0, fpscr" : "=r"(r) ::: "volatile");
+            }
+            Fpscr { bits: r }
+        }
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => unsafe {
+            extern "C" {
+                fn __get_FPSCR() -> u32;
+            }
+
+            Fpscr { bits: __get_FPSCR() }
+        },
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
+/// Set the value of the FPSCR register
+pub unsafe fn write(value: u32) {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => {
+            unsafe {
+                llvm_asm!("vmrs fpscr, $0" :: "r"(value) :: "volatile");
+            }
+        }
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => unsafe {
+            extern "C" {
+                fn __set_FPSCR(value: u32);
+            }
+
+            __set_FPSCR(value);
+        },
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
diff --git a/src/register/mod.rs b/src/register/mod.rs
index d69c1a5..efbe6ef 100644
--- a/src/register/mod.rs
+++ b/src/register/mod.rs
@@ -22,6 +22,10 @@
 //! - BASEPRI
 //! - FAULTMASK
 //!
+//! The following registers are only available for devices with an FPU:
+//!
+//! - FPSCR
+//!
 //! # References
 //!
 //! - Cortex-M* Devices Generic User Guide - Section 2.1.3 Core registers
@@ -37,6 +41,9 @@ pub mod control;
 #[cfg(all(not(armv6m), not(armv8m_base)))]
 pub mod faultmask;
 
+#[cfg(has_fpu)]
+pub mod fpscr;
+
 pub mod msp;
 
 pub mod primask;
-- 
cgit v1.2.3


From 088972af32d85abea570339d8b143649998aa96c Mon Sep 17 00:00:00 2001
From: Dániel Buga <daniel@revolutionrobotics.org>
Date: Wed, 27 May 2020 23:24:07 +0200
Subject: Add doc comments

---
 src/register/fpscr.rs | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'src')

diff --git a/src/register/fpscr.rs b/src/register/fpscr.rs
index 22f6ce1..3ae6248 100644
--- a/src/register/fpscr.rs
+++ b/src/register/fpscr.rs
@@ -1,11 +1,13 @@
 //! Floating-point Status Control Register
 
+/// Floating-point Status Control Register
 #[allow(clippy::missing_inline_in_public_items)]
 #[derive(Clone, Copy, Debug)]
 pub struct Fpscr {
     bits: u32,
 }
 
+//! Rounding mode
 #[derive(Clone, Copy, Debug)]
 pub enum RMode {
     Nearest,
@@ -45,21 +47,25 @@ impl Fpscr {
         self.bits & (1 << 28) != 0
     }
 
+    //! Read the Alternative Half Precision bit
     #[inline]
     pub fn ahp(self) -> bool {
         if self.bits & (1 << 26) != 0
     }
 
+    //! Read the Default NaN mode bit
     #[inline]
     pub fn dn(self) -> bool {
         if self.bits & (1 << 25) != 0
     }
 
+    //! Read the Flush to Zero mode bit
     #[inline]
     pub fn fz(self) -> bool {
         if self.bits & (1 << 24) != 0
     }
 
+    //! Read the Rounding Mode control field
     #[inline]
     pub fn rmode(self) -> RMode {
         match self.bits & (3 << 22) {
@@ -70,31 +76,37 @@ impl Fpscr {
         }
     }
 
+    //! Read the Input Denormal cumulative exception bit
     #[inline]
     pub fn idc(self) -> bool {
         if self.bits & (1 << 7) != 0
     }
 
+    //! Read the Inexact cumulative exception bit
     #[inline]
     pub fn ixc(self) -> bool {
         if self.bits & (1 << 4) != 0
     }
 
+    //! Read the Underflow cumulative exception bit
     #[inline]
     pub fn ufc(self) -> bool {
         if self.bits & (1 << 3) != 0
     }
 
+    //! Read the Overflow cumulative exception bit
     #[inline]
     pub fn ofc(self) -> bool {
         if self.bits & (1 << 2) != 0
     }
 
+    //! Read the Division by Zero cumulative exception bit
     #[inline]
     pub fn dzc(self) -> bool {
         if self.bits & (1 << 1) != 0
     }
 
+    //! Read the Invalid Operation cumulative exception bit
     #[inline]
     pub fn ioc(self) -> bool {
         if self.bits & (1 << 0) != 0
-- 
cgit v1.2.3


From 3e3213b771852c857b567f5806656073035997ba Mon Sep 17 00:00:00 2001
From: Dániel Buga <daniel@revolutionrobotics.org>
Date: Thu, 28 May 2020 00:04:28 +0200
Subject: Fix store instructions

---
 asm-fpu.s             | 2 +-
 src/register/fpscr.rs | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/asm-fpu.s b/asm-fpu.s
index 4700369..417d199 100644
--- a/asm-fpu.s
+++ b/asm-fpu.s
@@ -15,7 +15,7 @@ __get_FPSCR:
   .thumb_func
   .cfi_startproc
 __set_FPSCR:
-  vmrs fpscr, r0
+  vmsr fpscr, r0
   bx lr
   .cfi_endproc
   .size __set_FPSCR, . - __set_FPSCR
diff --git a/src/register/fpscr.rs b/src/register/fpscr.rs
index 3ae6248..25fa2dc 100644
--- a/src/register/fpscr.rs
+++ b/src/register/fpscr.rs
@@ -145,7 +145,7 @@ pub unsafe fn write(value: u32) {
         #[cfg(all(cortex_m, feature = "inline-asm"))]
         () => {
             unsafe {
-                llvm_asm!("vmrs fpscr, $0" :: "r"(value) :: "volatile");
+                llvm_asm!("vmsr fpscr, $0" :: "r"(value) :: "volatile");
             }
         }
 
-- 
cgit v1.2.3


From bc0db25e6a9308bb4340dcce7f5d53151b0b728d Mon Sep 17 00:00:00 2001
From: Dániel Buga <daniel@revolutionrobotics.org>
Date: Thu, 28 May 2020 00:10:02 +0200
Subject: Fix doc comments

---
 src/register/fpscr.rs | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

(limited to 'src')

diff --git a/src/register/fpscr.rs b/src/register/fpscr.rs
index 25fa2dc..4017956 100644
--- a/src/register/fpscr.rs
+++ b/src/register/fpscr.rs
@@ -7,7 +7,7 @@ pub struct Fpscr {
     bits: u32,
 }
 
-//! Rounding mode
+/// Rounding mode
 #[derive(Clone, Copy, Debug)]
 pub enum RMode {
     Nearest,
@@ -23,49 +23,49 @@ impl Fpscr {
         self.bits
     }
 
-    //! Read the Negative condition code flag
+    /// Read the Negative condition code flag
     #[inline]
     pub fn n(self) -> bool {
         self.bits & (1 << 31) != 0
     }
 
-    //! Read the Zero condition code flag
+    /// Read the Zero condition code flag
     #[inline]
     pub fn z(self) -> bool {
         self.bits & (1 << 30) != 0
     }
 
-    //! Read the Carry condition code flag
+    /// Read the Carry condition code flag
     #[inline]
     pub fn c(self) -> bool {
         self.bits & (1 << 29) != 0
     }
 
-    //! Read the Overflow condition code flag
+    /// Read the Overflow condition code flag
     #[inline]
     pub fn v(self) -> bool {
         self.bits & (1 << 28) != 0
     }
 
-    //! Read the Alternative Half Precision bit
+    /// Read the Alternative Half Precision bit
     #[inline]
     pub fn ahp(self) -> bool {
         if self.bits & (1 << 26) != 0
     }
 
-    //! Read the Default NaN mode bit
+    /// Read the Default NaN mode bit
     #[inline]
     pub fn dn(self) -> bool {
         if self.bits & (1 << 25) != 0
     }
 
-    //! Read the Flush to Zero mode bit
+    /// Read the Flush to Zero mode bit
     #[inline]
     pub fn fz(self) -> bool {
         if self.bits & (1 << 24) != 0
     }
 
-    //! Read the Rounding Mode control field
+    /// Read the Rounding Mode control field
     #[inline]
     pub fn rmode(self) -> RMode {
         match self.bits & (3 << 22) {
@@ -76,37 +76,37 @@ impl Fpscr {
         }
     }
 
-    //! Read the Input Denormal cumulative exception bit
+    /// Read the Input Denormal cumulative exception bit
     #[inline]
     pub fn idc(self) -> bool {
         if self.bits & (1 << 7) != 0
     }
 
-    //! Read the Inexact cumulative exception bit
+    /// Read the Inexact cumulative exception bit
     #[inline]
     pub fn ixc(self) -> bool {
         if self.bits & (1 << 4) != 0
     }
 
-    //! Read the Underflow cumulative exception bit
+    /// Read the Underflow cumulative exception bit
     #[inline]
     pub fn ufc(self) -> bool {
         if self.bits & (1 << 3) != 0
     }
 
-    //! Read the Overflow cumulative exception bit
+    /// Read the Overflow cumulative exception bit
     #[inline]
     pub fn ofc(self) -> bool {
         if self.bits & (1 << 2) != 0
     }
 
-    //! Read the Division by Zero cumulative exception bit
+    /// Read the Division by Zero cumulative exception bit
     #[inline]
     pub fn dzc(self) -> bool {
         if self.bits & (1 << 1) != 0
     }
 
-    //! Read the Invalid Operation cumulative exception bit
+    /// Read the Invalid Operation cumulative exception bit
     #[inline]
     pub fn ioc(self) -> bool {
         if self.bits & (1 << 0) != 0
-- 
cgit v1.2.3


From 53b79bd8bbf449262520f78e4a575af10bebdc69 Mon Sep 17 00:00:00 2001
From: Dániel Buga <daniel@revolutionrobotics.org>
Date: Thu, 28 May 2020 00:16:10 +0200
Subject: Where did those ifs come from...

---
 src/register/fpscr.rs | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

(limited to 'src')

diff --git a/src/register/fpscr.rs b/src/register/fpscr.rs
index 4017956..d7ceea2 100644
--- a/src/register/fpscr.rs
+++ b/src/register/fpscr.rs
@@ -50,19 +50,19 @@ impl Fpscr {
     /// Read the Alternative Half Precision bit
     #[inline]
     pub fn ahp(self) -> bool {
-        if self.bits & (1 << 26) != 0
+        self.bits & (1 << 26) != 0
     }
 
     /// Read the Default NaN mode bit
     #[inline]
     pub fn dn(self) -> bool {
-        if self.bits & (1 << 25) != 0
+        self.bits & (1 << 25) != 0
     }
 
     /// Read the Flush to Zero mode bit
     #[inline]
     pub fn fz(self) -> bool {
-        if self.bits & (1 << 24) != 0
+        self.bits & (1 << 24) != 0
     }
 
     /// Read the Rounding Mode control field
@@ -79,37 +79,37 @@ impl Fpscr {
     /// Read the Input Denormal cumulative exception bit
     #[inline]
     pub fn idc(self) -> bool {
-        if self.bits & (1 << 7) != 0
+        self.bits & (1 << 7) != 0
     }
 
     /// Read the Inexact cumulative exception bit
     #[inline]
     pub fn ixc(self) -> bool {
-        if self.bits & (1 << 4) != 0
+        self.bits & (1 << 4) != 0
     }
 
     /// Read the Underflow cumulative exception bit
     #[inline]
     pub fn ufc(self) -> bool {
-        if self.bits & (1 << 3) != 0
+        self.bits & (1 << 3) != 0
     }
 
     /// Read the Overflow cumulative exception bit
     #[inline]
     pub fn ofc(self) -> bool {
-        if self.bits & (1 << 2) != 0
+        self.bits & (1 << 2) != 0
     }
 
     /// Read the Division by Zero cumulative exception bit
     #[inline]
     pub fn dzc(self) -> bool {
-        if self.bits & (1 << 1) != 0
+        self.bits & (1 << 1) != 0
     }
 
     /// Read the Invalid Operation cumulative exception bit
     #[inline]
     pub fn ioc(self) -> bool {
-        if self.bits & (1 << 0) != 0
+        self.bits & (1 << 0) != 0
     }
 }
 
-- 
cgit v1.2.3


From 513ffd47e65f4e250eb099da4660d474cd4dac29 Mon Sep 17 00:00:00 2001
From: Dániel Buga <daniel@revolutionrobotics.org>
Date: Thu, 28 May 2020 00:30:19 +0200
Subject: Fix remaining compiler sadness

---
 src/register/fpscr.rs | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

(limited to 'src')

diff --git a/src/register/fpscr.rs b/src/register/fpscr.rs
index d7ceea2..057b145 100644
--- a/src/register/fpscr.rs
+++ b/src/register/fpscr.rs
@@ -10,9 +10,13 @@ pub struct Fpscr {
 /// Rounding mode
 #[derive(Clone, Copy, Debug)]
 pub enum RMode {
+    /// Round to Nearest (RN) mode. This is the reset value.
     Nearest,
+    /// Round towards Plus Infinity (RP) mode.
     PlusInfinity,
+    /// Round towards Minus Infinity (RM) mode.
     MinusInfinity,
+    /// Round towards Zero (RZ) mode.
     Zero,
 }
 
@@ -68,11 +72,11 @@ impl Fpscr {
     /// Read the Rounding Mode control field
     #[inline]
     pub fn rmode(self) -> RMode {
-        match self.bits & (3 << 22) {
-            0 << 22 => RMode::Nearest,
-            1 << 22 => RMode::PlusInfinity,
-            2 << 22 => RMode::MinusInfinity,
-            3 << 22 => RMode::Zero,
+        match (self.bits & (3 << 22)) >> 22 {
+            0 => RMode::Nearest,
+            1 => RMode::PlusInfinity,
+            2 => RMode::MinusInfinity,
+            _ => RMode::Zero,
         }
     }
 
-- 
cgit v1.2.3


From 3cb2102c1fddca88f3ee687210203e1cd93531f7 Mon Sep 17 00:00:00 2001
From: Dániel Buga <daniel@revolutionrobotics.org>
Date: Thu, 28 May 2020 00:38:35 +0200
Subject: Stylistic updates, add from_bits

---
 src/register/fpscr.rs | 28 +++++++++++++++++-----------
 1 file changed, 17 insertions(+), 11 deletions(-)

(limited to 'src')

diff --git a/src/register/fpscr.rs b/src/register/fpscr.rs
index 057b145..cde2e4b 100644
--- a/src/register/fpscr.rs
+++ b/src/register/fpscr.rs
@@ -21,6 +21,12 @@ pub enum RMode {
 }
 
 impl Fpscr {
+    /// Creates a `Fspcr` value from raw bits.
+    #[inline]
+    pub fn from_bits(bits: u32) -> Self {
+        Self { bits }
+    }
+
     /// Returns the contents of the register as raw bits
     #[inline]
     pub fn bits(self) -> u32 {
@@ -118,6 +124,7 @@ impl Fpscr {
 }
 
 /// Read the FPSCR register
+#[inline]
 pub fn read() -> Fpscr {
     match () {
         #[cfg(all(cortex_m, feature = "inline-asm"))]
@@ -126,7 +133,7 @@ pub fn read() -> Fpscr {
             unsafe {
                 llvm_asm!("vmrs $0, fpscr" : "=r"(r) ::: "volatile");
             }
-            Fpscr { bits: r }
+            Fpscr::from_bits(r)
         }
 
         #[cfg(all(cortex_m, not(feature = "inline-asm")))]
@@ -134,8 +141,7 @@ pub fn read() -> Fpscr {
             extern "C" {
                 fn __get_FPSCR() -> u32;
             }
-
-            Fpscr { bits: __get_FPSCR() }
+            Fpscr::from_bits(__get_FPSCR())
         },
 
         #[cfg(not(cortex_m))]
@@ -144,23 +150,23 @@ pub fn read() -> Fpscr {
 }
 
 /// Set the value of the FPSCR register
-pub unsafe fn write(value: u32) {
+#[inline]
+pub unsafe fn write(_fspcr: Fpscr) {
     match () {
         #[cfg(all(cortex_m, feature = "inline-asm"))]
         () => {
-            unsafe {
-                llvm_asm!("vmsr fpscr, $0" :: "r"(value) :: "volatile");
-            }
+            let bits = _fspcr.bits();
+            llvm_asm!("vmsr fpscr, $0" :: "r"(bits) :: "volatile");
         }
 
         #[cfg(all(cortex_m, not(feature = "inline-asm")))]
-        () => unsafe {
+        () => {
             extern "C" {
-                fn __set_FPSCR(value: u32);
+                fn __set_FPSCR(bits: u32);
             }
 
-            __set_FPSCR(value);
-        },
+            __set_FPSCR(_fspcr.bits());
+        }
 
         #[cfg(not(cortex_m))]
         () => unimplemented!(),
-- 
cgit v1.2.3


From 7767dac7ec005c281344a225f36870d83bc7e226 Mon Sep 17 00:00:00 2001
From: Dániel Buga <daniel@revolutionrobotics.org>
Date: Sat, 6 Jun 2020 18:33:24 +0200
Subject: Implement bit manipulation methods

---
 src/register/fpscr.rs | 128 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 128 insertions(+)

(limited to 'src')

diff --git a/src/register/fpscr.rs b/src/register/fpscr.rs
index cde2e4b..79ddd3b 100644
--- a/src/register/fpscr.rs
+++ b/src/register/fpscr.rs
@@ -39,42 +39,105 @@ impl Fpscr {
         self.bits & (1 << 31) != 0
     }
 
+    /// Sets the Negative condition code flag
+    pub fn set_n(&mut self, n: bool) {
+        let mask = 1 << 31;
+        match n {
+            true => self.bits |= mask,
+            false => self.bits &= !mask,
+        }
+    }
+
     /// Read the Zero condition code flag
     #[inline]
     pub fn z(self) -> bool {
         self.bits & (1 << 30) != 0
     }
 
+    /// Sets the Zero condition code flag
+    pub fn set_z(&mut self, z: bool) {
+        let mask = 1 << 30;
+        match z {
+            true => self.bits |= mask,
+            false => self.bits &= !mask,
+        }
+    }
+
     /// Read the Carry condition code flag
     #[inline]
     pub fn c(self) -> bool {
         self.bits & (1 << 29) != 0
     }
 
+    /// Sets the Carry condition code flag
+    pub fn set_c(&mut self, c: bool) {
+        let mask = 1 << 29;
+        match c {
+            true => self.bits |= mask,
+            false => self.bits &= !mask,
+        }
+    }
+
     /// Read the Overflow condition code flag
     #[inline]
     pub fn v(self) -> bool {
         self.bits & (1 << 28) != 0
     }
 
+    /// Sets the Zero condition code flag
+    pub fn set_v(&mut self, v: bool) {
+        let mask = 1 << 28;
+        match v {
+            true => self.bits |= mask,
+            false => self.bits &= !mask,
+        }
+    }
+
     /// Read the Alternative Half Precision bit
     #[inline]
     pub fn ahp(self) -> bool {
         self.bits & (1 << 26) != 0
     }
 
+    /// Sets the Alternative Half Precision bit
+    pub fn set_ahp(&mut self, ahp: bool) {
+        let mask = 1 << 26;
+        match ahp {
+            true => self.bits |= mask,
+            false => self.bits &= !mask,
+        }
+    }
+
     /// Read the Default NaN mode bit
     #[inline]
     pub fn dn(self) -> bool {
         self.bits & (1 << 25) != 0
     }
 
+    /// Sets the Default NaN mode bit
+    pub fn set_dn(&mut self, dn: bool) {
+        let mask = 1 << 25;
+        match dn {
+            true => self.bits |= mask,
+            false => self.bits &= !mask,
+        }
+    }
+
     /// Read the Flush to Zero mode bit
     #[inline]
     pub fn fz(self) -> bool {
         self.bits & (1 << 24) != 0
     }
 
+    /// Sets the Flush to Zero mode bit
+    pub fn set_fz(&mut self, fz: bool) {
+        let mask = 1 << 24;
+        match fz {
+            true => self.bits |= mask,
+            false => self.bits &= !mask,
+        }
+    }
+
     /// Read the Rounding Mode control field
     #[inline]
     pub fn rmode(self) -> RMode {
@@ -86,41 +149,106 @@ impl Fpscr {
         }
     }
 
+    /// Sets the Rounding Mode control field
+    pub fn set_rmode(&mut self, rmode: RMode) {
+        let mask = 3 << 22;
+        match rmode {
+            RMode::Nearest => self.bits = (self.bits & !mask),
+            RMode::Nearest => self.bits = (self.bits & !mask) | (1 << 22),
+            RMode::Nearest => self.bits = (self.bits & !mask) | (2 << 22),
+            RMode::Nearest => self.bits = self.bits | mask,
+        }
+    }
+
     /// Read the Input Denormal cumulative exception bit
     #[inline]
     pub fn idc(self) -> bool {
         self.bits & (1 << 7) != 0
     }
 
+    /// Sets the Input Denormal cumulative exception bit
+    pub fn set_idc(&mut self, idc: bool) {
+        let mask = 1 << 7;
+        match idc {
+            true => self.bits |= mask,
+            false => self.bits &= !mask,
+        }
+    }
+
     /// Read the Inexact cumulative exception bit
     #[inline]
     pub fn ixc(self) -> bool {
         self.bits & (1 << 4) != 0
     }
 
+    /// Sets the Inexact cumulative exception bit
+    pub fn set_ixc(&mut self, ixc: bool) {
+        let mask = 1 << 4;
+        match ixc {
+            true => self.bits |= mask,
+            false => self.bits &= !mask,
+        }
+    }
+
     /// Read the Underflow cumulative exception bit
     #[inline]
     pub fn ufc(self) -> bool {
         self.bits & (1 << 3) != 0
     }
 
+    /// Sets the Underflow cumulative exception bit
+    pub fn set_ufc(&mut self, ufc: bool) {
+        let mask = 1 << 3;
+        match ufc {
+            true => self.bits |= mask,
+            false => self.bits &= !mask,
+        }
+    }
+
     /// Read the Overflow cumulative exception bit
     #[inline]
     pub fn ofc(self) -> bool {
         self.bits & (1 << 2) != 0
     }
 
+    /// Sets the Overflow cumulative exception bit
+    pub fn set_ofc(&mut self, ofc: bool) {
+        let mask = 1 << 2;
+        match ofc {
+            true => self.bits |= mask,
+            false => self.bits &= !mask,
+        }
+    }
+
     /// Read the Division by Zero cumulative exception bit
     #[inline]
     pub fn dzc(self) -> bool {
         self.bits & (1 << 1) != 0
     }
 
+    /// Sets the Division by Zero cumulative exception bit
+    pub fn set_dzc(&mut self, dzc: bool) {
+        let mask = 1 << 1;
+        match dzc {
+            true => self.bits |= mask,
+            false => self.bits &= !mask,
+        }
+    }
+
     /// Read the Invalid Operation cumulative exception bit
     #[inline]
     pub fn ioc(self) -> bool {
         self.bits & (1 << 0) != 0
     }
+
+    /// Sets the Invalid Operation cumulative exception bit
+    pub fn set_ioc(&mut self, ioc: bool) {
+        let mask = 1 << 0;
+        match ioc {
+            true => self.bits |= mask,
+            false => self.bits &= !mask,
+        }
+    }
 }
 
 /// Read the FPSCR register
-- 
cgit v1.2.3


From 0d8723ef083cc87a217eb527218387f63de9c7ce Mon Sep 17 00:00:00 2001
From: Dániel Buga <daniel@revolutionrobotics.org>
Date: Sat, 6 Jun 2020 18:36:48 +0200
Subject: Add methods to RMode

---
 src/register/fpscr.rs | 52 ++++++++++++++++++++++++++++++++++++++-------------
 1 file changed, 39 insertions(+), 13 deletions(-)

(limited to 'src')

diff --git a/src/register/fpscr.rs b/src/register/fpscr.rs
index 79ddd3b..0baac32 100644
--- a/src/register/fpscr.rs
+++ b/src/register/fpscr.rs
@@ -7,19 +7,6 @@ pub struct Fpscr {
     bits: u32,
 }
 
-/// Rounding mode
-#[derive(Clone, Copy, Debug)]
-pub enum RMode {
-    /// Round to Nearest (RN) mode. This is the reset value.
-    Nearest,
-    /// Round towards Plus Infinity (RP) mode.
-    PlusInfinity,
-    /// Round towards Minus Infinity (RM) mode.
-    MinusInfinity,
-    /// Round towards Zero (RZ) mode.
-    Zero,
-}
-
 impl Fpscr {
     /// Creates a `Fspcr` value from raw bits.
     #[inline]
@@ -251,6 +238,45 @@ impl Fpscr {
     }
 }
 
+/// Rounding mode
+#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+pub enum RMode {
+    /// Round to Nearest (RN) mode. This is the reset value.
+    Nearest,
+    /// Round towards Plus Infinity (RP) mode.
+    PlusInfinity,
+    /// Round towards Minus Infinity (RM) mode.
+    MinusInfinity,
+    /// Round towards Zero (RZ) mode.
+    Zero,
+}
+
+impl RMode {
+    /// Is Nearest the current rounding mode?
+    #[inline]
+    fn is_nearest(self) -> bool {
+        self == RMode::Nearest
+    }
+
+    /// Is Plus Infinity the current rounding mode?
+    #[inline]
+    fn is_plus_infinity(self) -> bool {
+        self == RMode::PlusInfinity
+    }
+
+    /// Is Minus Infinity the current rounding mode?
+    #[inline]
+    fn is_minus_infinity(self) -> bool {
+        self == RMode::MinusInfinity
+    }
+
+    /// Is Zero the current rounding mode?
+    #[inline]
+    fn is_zero(self) -> bool {
+        self == RMode::Zero
+    }
+}
+
 /// Read the FPSCR register
 #[inline]
 pub fn read() -> Fpscr {
-- 
cgit v1.2.3


From 3d7648ffc9a1111cf5bab22d5807c155d9610865 Mon Sep 17 00:00:00 2001
From: Dániel Buga <daniel@revolutionrobotics.org>
Date: Sat, 6 Jun 2020 18:47:23 +0200
Subject: Oops. Fix pattern matching

---
 src/register/fpscr.rs | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'src')

diff --git a/src/register/fpscr.rs b/src/register/fpscr.rs
index 0baac32..9d78eff 100644
--- a/src/register/fpscr.rs
+++ b/src/register/fpscr.rs
@@ -140,10 +140,10 @@ impl Fpscr {
     pub fn set_rmode(&mut self, rmode: RMode) {
         let mask = 3 << 22;
         match rmode {
-            RMode::Nearest => self.bits = (self.bits & !mask),
-            RMode::Nearest => self.bits = (self.bits & !mask) | (1 << 22),
-            RMode::Nearest => self.bits = (self.bits & !mask) | (2 << 22),
-            RMode::Nearest => self.bits = self.bits | mask,
+            RMode::Nearest => self.bits = self.bits & !mask,
+            RMode::PlusInfinity => self.bits = (self.bits & !mask) | (1 << 22),
+            RMode::MinusInfinity => self.bits = (self.bits & !mask) | (2 << 22),
+            RMode::Zero => self.bits = self.bits | mask,
         }
     }
 
-- 
cgit v1.2.3


From 37e6543330c90bc0f4b417351be91b344a165a2e Mon Sep 17 00:00:00 2001
From: Dániel Buga <daniel@revolutionrobotics.org>
Date: Sat, 6 Jun 2020 18:58:02 +0200
Subject: Add missing #[inline]s

---
 src/register/fpscr.rs | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

(limited to 'src')

diff --git a/src/register/fpscr.rs b/src/register/fpscr.rs
index 9d78eff..8de237a 100644
--- a/src/register/fpscr.rs
+++ b/src/register/fpscr.rs
@@ -27,6 +27,7 @@ impl Fpscr {
     }
 
     /// Sets the Negative condition code flag
+    #[inline]
     pub fn set_n(&mut self, n: bool) {
         let mask = 1 << 31;
         match n {
@@ -42,6 +43,7 @@ impl Fpscr {
     }
 
     /// Sets the Zero condition code flag
+    #[inline]
     pub fn set_z(&mut self, z: bool) {
         let mask = 1 << 30;
         match z {
@@ -57,6 +59,7 @@ impl Fpscr {
     }
 
     /// Sets the Carry condition code flag
+    #[inline]
     pub fn set_c(&mut self, c: bool) {
         let mask = 1 << 29;
         match c {
@@ -72,6 +75,7 @@ impl Fpscr {
     }
 
     /// Sets the Zero condition code flag
+    #[inline]
     pub fn set_v(&mut self, v: bool) {
         let mask = 1 << 28;
         match v {
@@ -87,6 +91,7 @@ impl Fpscr {
     }
 
     /// Sets the Alternative Half Precision bit
+    #[inline]
     pub fn set_ahp(&mut self, ahp: bool) {
         let mask = 1 << 26;
         match ahp {
@@ -102,6 +107,7 @@ impl Fpscr {
     }
 
     /// Sets the Default NaN mode bit
+    #[inline]
     pub fn set_dn(&mut self, dn: bool) {
         let mask = 1 << 25;
         match dn {
@@ -117,6 +123,7 @@ impl Fpscr {
     }
 
     /// Sets the Flush to Zero mode bit
+    #[inline]
     pub fn set_fz(&mut self, fz: bool) {
         let mask = 1 << 24;
         match fz {
@@ -137,6 +144,7 @@ impl Fpscr {
     }
 
     /// Sets the Rounding Mode control field
+    #[inline]
     pub fn set_rmode(&mut self, rmode: RMode) {
         let mask = 3 << 22;
         match rmode {
@@ -154,6 +162,7 @@ impl Fpscr {
     }
 
     /// Sets the Input Denormal cumulative exception bit
+    #[inline]
     pub fn set_idc(&mut self, idc: bool) {
         let mask = 1 << 7;
         match idc {
@@ -169,6 +178,7 @@ impl Fpscr {
     }
 
     /// Sets the Inexact cumulative exception bit
+    #[inline]
     pub fn set_ixc(&mut self, ixc: bool) {
         let mask = 1 << 4;
         match ixc {
@@ -184,6 +194,7 @@ impl Fpscr {
     }
 
     /// Sets the Underflow cumulative exception bit
+    #[inline]
     pub fn set_ufc(&mut self, ufc: bool) {
         let mask = 1 << 3;
         match ufc {
@@ -199,6 +210,7 @@ impl Fpscr {
     }
 
     /// Sets the Overflow cumulative exception bit
+    #[inline]
     pub fn set_ofc(&mut self, ofc: bool) {
         let mask = 1 << 2;
         match ofc {
@@ -214,6 +226,7 @@ impl Fpscr {
     }
 
     /// Sets the Division by Zero cumulative exception bit
+    #[inline]
     pub fn set_dzc(&mut self, dzc: bool) {
         let mask = 1 << 1;
         match dzc {
@@ -229,6 +242,7 @@ impl Fpscr {
     }
 
     /// Sets the Invalid Operation cumulative exception bit
+    #[inline]
     pub fn set_ioc(&mut self, ioc: bool) {
         let mask = 1 << 0;
         match ioc {
-- 
cgit v1.2.3


From 7c9afcca584c37d6b8ed4af2c81cefb766a6201e Mon Sep 17 00:00:00 2001
From: Dániel Buga <daniel@revolutionrobotics.org>
Date: Sat, 6 Jun 2020 18:58:28 +0200
Subject: Make RMode methods actually accessible

---
 src/register/fpscr.rs | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'src')

diff --git a/src/register/fpscr.rs b/src/register/fpscr.rs
index 8de237a..7d8ea1a 100644
--- a/src/register/fpscr.rs
+++ b/src/register/fpscr.rs
@@ -268,25 +268,25 @@ pub enum RMode {
 impl RMode {
     /// Is Nearest the current rounding mode?
     #[inline]
-    fn is_nearest(self) -> bool {
+    pub fn is_nearest(self) -> bool {
         self == RMode::Nearest
     }
 
     /// Is Plus Infinity the current rounding mode?
     #[inline]
-    fn is_plus_infinity(self) -> bool {
+    pub fn is_plus_infinity(self) -> bool {
         self == RMode::PlusInfinity
     }
 
     /// Is Minus Infinity the current rounding mode?
     #[inline]
-    fn is_minus_infinity(self) -> bool {
+    pub fn is_minus_infinity(self) -> bool {
         self == RMode::MinusInfinity
     }
 
     /// Is Zero the current rounding mode?
     #[inline]
-    fn is_zero(self) -> bool {
+    pub fn is_zero(self) -> bool {
         self == RMode::Zero
     }
 }
-- 
cgit v1.2.3


From 4f22ee10bb1689b4622dd956daa0ee6c70781b40 Mon Sep 17 00:00:00 2001
From: Dániel Buga <daniel@revolutionrobotics.org>
Date: Sat, 6 Jun 2020 19:02:02 +0200
Subject: Add #[allow(clippy::missing_inline_in_public_items)] for consistency

---
 src/register/fpscr.rs | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src')

diff --git a/src/register/fpscr.rs b/src/register/fpscr.rs
index 7d8ea1a..569d3a7 100644
--- a/src/register/fpscr.rs
+++ b/src/register/fpscr.rs
@@ -253,6 +253,7 @@ impl Fpscr {
 }
 
 /// Rounding mode
+#[allow(clippy::missing_inline_in_public_items)]
 #[derive(Clone, Copy, Debug, Eq, PartialEq)]
 pub enum RMode {
     /// Round to Nearest (RN) mode. This is the reset value.
-- 
cgit v1.2.3