From 733e6d6f1bbd99346d74f8d23310065335f4f04c Mon Sep 17 00:00:00 2001 From: Rajiv Ranganath Date: Fri, 13 Jul 2018 19:52:38 +0530 Subject: Rename `shcrs` to `shcsr` in `scb::RegisterBlock` Commit `c290aa4e` introduced `shcrs` field to `scb::RegisterBlock`. In CMSIS, this field is `shcsr`. https://github.com/ARM-software/CMSIS_5/blob/5.3.0/CMSIS/Core/Include/core_cm4.h#L449 This patch changes `shcrs` to `shcsr`. Signed-off-by: Rajiv Ranganath --- src/peripheral/scb.rs | 2 +- src/peripheral/test.rs | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs index 2ad0770..ba36093 100644 --- a/src/peripheral/scb.rs +++ b/src/peripheral/scb.rs @@ -51,7 +51,7 @@ pub struct RegisterBlock { pub shpr: [RW; 2], /// System Handler Control and State - pub shcrs: RW, + pub shcsr: RW, /// Configurable Fault Status (not present on Cortex-M0 variants) #[cfg(not(armv6m))] diff --git a/src/peripheral/test.rs b/src/peripheral/test.rs index cc3e292..1f75818 100644 --- a/src/peripheral/test.rs +++ b/src/peripheral/test.rs @@ -121,7 +121,7 @@ fn scb() { assert_eq!(address(&scb.scr), 0xE000_ED10); assert_eq!(address(&scb.ccr), 0xE000_ED14); assert_eq!(address(&scb.shpr), 0xE000_ED18); - assert_eq!(address(&scb.shcrs), 0xE000_ED24); + assert_eq!(address(&scb.shcsr), 0xE000_ED24); assert_eq!(address(&scb.cfsr), 0xE000_ED28); assert_eq!(address(&scb.hfsr), 0xE000_ED2C); assert_eq!(address(&scb.dfsr), 0xE000_ED30); -- cgit v1.2.3