From 771fc84d6ea9d669848baf6acff9e54b36819eb1 Mon Sep 17 00:00:00 2001
From: Brandon Matthews <bmatthews@optimaltour.us>
Date: Tue, 12 Mar 2019 14:20:56 -0700
Subject: Fix STIR register test, remove armv6m-related offsets in NVIC

---
 src/peripheral/nvic.rs | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

(limited to 'src')

diff --git a/src/peripheral/nvic.rs b/src/peripheral/nvic.rs
index a81fa6d..57ce009 100644
--- a/src/peripheral/nvic.rs
+++ b/src/peripheral/nvic.rs
@@ -1,8 +1,8 @@
 //! Nested Vector Interrupt Controller
 
+use volatile_register::RW;
 #[cfg(not(armv6m))]
 use volatile_register::{RO, WO};
-use volatile_register::RW;
 
 use interrupt::Nr;
 use peripheral::NVIC;
@@ -67,10 +67,7 @@ pub struct RegisterBlock {
     pub ipr: [RW<u32>; 8],
 
     #[cfg(not(armv6m))]
-    reserved5: [u32; 208],
-
-    #[cfg(armv6m)]
-    reserved5: [u32; 696],
+    _reserved6: [u32; 580],
 
     #[cfg(not(armv6m))]
     /// Software Trigger Interrupt
-- 
cgit v1.2.3