From f72a289c9ddc493c22a8fe4f8f6b5dedc82a48a1 Mon Sep 17 00:00:00 2001 From: Abe Kohandel Date: Sun, 2 Sep 2018 14:54:56 -0700 Subject: Add PendSV exception set and clear to SCB --- src/peripheral/scb.rs | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'src') diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs index d26e0a6..939d5a7 100644 --- a/src/peripheral/scb.rs +++ b/src/peripheral/scb.rs @@ -615,3 +615,29 @@ impl SCB { } } } + +const SCB_ICSR_PENDSVSET: u32 = 1 << 28; +const SCB_ICSR_PENDSVCLR: u32 = 1 << 27; + +impl SCB { + /// Set the PENDSVSET bit in the ICSR register which will pend the PendSV interrupt + pub fn set_pendsv() { + unsafe { + (*Self::ptr()).icsr.write(SCB_ICSR_PENDSVSET); + } + } + + /// Check if PENDSVSET bit in the ICSR register is set meaning PendSV interrupt is pending + pub fn is_pendsv_pending() -> bool { + unsafe { + (*Self::ptr()).icsr.read() & SCB_ICSR_PENDSVSET == SCB_ICSR_PENDSVSET + } + } + + /// Set the PENDSVCLR bit in the ICSR register which will clear a pending PendSV interrupt + pub fn clear_pendsv() { + unsafe { + (*Self::ptr()).icsr.write(SCB_ICSR_PENDSVCLR); + } + } +} -- cgit v1.2.3