Merge #652

652: Remove use of basepri register on thumbv8m.base r=AfoHT a=neonquill

The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error:

```
error[E0432]: unresolved import `cortex_m::register::basepri`
  --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5
   |
25 | use cortex_m::register::basepri;
   |     ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register`
```

I wasn't sure if it made more sense to replace the `armv7m` config flag with something related to basepri availability or to get closer to matching the cortex-m use of several architecture specific flags. In the end i chose to make the minimal change possible and just narrowed the existing `thumbv8m` check.

Context:
[cortex-m:src/register/mod.rs](https://github.com/rust-embedded/cortex-m/blob/4e908625204a1e95dd3fd5bdcd8d66d6bc11c3bc/src/register/mod.rs#L33):
```
#[cfg(all(not(armv6m), not(armv8m_base)))]
pub mod basepri;
```

[cortex-m:build.rs](https://github.com/rust-embedded/cortex-m/blob/4e908625204a1e95dd3fd5bdcd8d66d6bc11c3bc/build.rs#L21):
```
    } else if target.starts_with("thumbv8m.base") {
        println!("cargo:rustc-cfg=cortex_m");
        println!("cargo:rustc-cfg=armv8m");
        println!("cargo:rustc-cfg=armv8m_base");
```

Co-authored-by: David Watson <david@neonquill.com>

1 files changed, 6 insertions, 5 deletions

diff --git a/macros/src/codegen/assertions.rs b/macros/src/codegen/assertions.rs
index f6a098b5..66e54095 100644
--- a/macros/src/codegen/assertions.rs
+++ b/macros/src/codegen/assertions.rs
@@ -22,15 +22,16 @@ pub fn codegen(app: &App, analysis: &Analysis, extra: &Extra) -> Vec<TokenStream
     }
 
     let device = &extra.device;
-    let arm_v6_checks: Vec<_> = app
+    let chunks_name = util::priority_mask_chunks_ident();
+    let no_basepri_checks: Vec<_> = app
         .hardware_tasks
         .iter()
         .filter_map(|(_, task)| {
             if !util::is_exception(&task.args.binds) {
                 let interrupt_name = &task.args.binds;
                 Some(quote!(
-                    if (#device::Interrupt::#interrupt_name as u32) > 31 {
-                        ::core::panic!("An interrupt above value 31 is used while in armv6");
+                    if (#device::Interrupt::#interrupt_name as usize) >= (#chunks_name * 32) {
+                        ::core::panic!("An interrupt out of range is used while in armv6 or armv8m.base");
                     }
                 ))
             } else {
@@ -41,8 +42,8 @@ pub fn codegen(app: &App, analysis: &Analysis, extra: &Extra) -> Vec<TokenStream
 
     let const_check = quote! {
         const _CONST_CHECK: () = {
-            if rtic::export::is_armv6() {
-                #(#arm_v6_checks)*
+            if !rtic::export::have_basepri() {
+                #(#no_basepri_checks)*
             } else {
                 // TODO: Add armv7 checks here
             }