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| author |  bors[bot] <26634292+bors[bot]@users.noreply.github.com>
| 2020-10-15 16:05:45 +0000 |
|---|---|---|
| committer |  GitHub <noreply@github.com>
| 2020-10-15 16:05:45 +0000 |
| commit | f9303cef1cf5b2d57d26e7667289fbdccf959ea8 (patch) | |
| tree | ec8fff4991a6547466df0d1d61ad7602eb58c38e /macros/src/codegen/schedule.rs | |
| parent | 1cda9eaeccbfd9b008bfa40b54b127a2bfa5324e (diff) | |
| parent | 7a57f1686063fec31d9a04678bd997ab57c91b7b (diff) | |
| download | rtic-f9303cef1cf5b2d57d26e7667289fbdccf959ea8.tar.gz rtic-f9303cef1cf5b2d57d26e7667289fbdccf959ea8.tar.zst rtic-f9303cef1cf5b2d57d26e7667289fbdccf959ea8.zip | |
Merge #395
395: Made relation between priority and number explicit r=korken89 a=diondokter
When quickly reading through the priorities chapter, I couldn't find in which order the priorities were, so I assumed it was the same as in the hardware.
In the cortex-m hardware, interrupts with the **lower** priority number will preempt the other interrupts.
RTIC does the reverse, so I think it's good to be more explicit about it.
Co-authored-by: Dion Dokter <diondokter@gmail.com>
Diffstat (limited to 'macros/src/codegen/schedule.rs')
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