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author | 2018-01-11 19:57:17 +0000 | |
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committer | 2018-01-11 19:57:17 +0000 | |
commit | 34edc41e9289e83468f68663a7f4a7f0f6cc2797 (patch) | |
tree | 128911a00f60bb7c0dc9c6ceb8c87e80e3935a99 /src/examples/_1_one_task.rs | |
parent | dd12a6a14d2bb028c8da96cb510b67de31d28be4 (diff) | |
parent | 1be43fc489993e63577515063ceb8a83b14423b8 (diff) | |
download | rtic-release/v0.2.tar.gz rtic-release/v0.2.tar.zst rtic-release/v0.2.zip |
Auto merge of #63 - japaric:cortex-m-up, r=japaricrelease/v0.2
adapt to changes in the cortex-m crate
None
Diffstat (limited to '')
-rw-r--r-- | src/examples/_1_one_task.rs | 43 |
1 files changed, 26 insertions, 17 deletions
diff --git a/src/examples/_1_one_task.rs b/src/examples/_1_one_task.rs index 614db2aa..c9004e86 100644 --- a/src/examples/_1_one_task.rs +++ b/src/examples/_1_one_task.rs @@ -2,6 +2,7 @@ //! //! ``` //! #![deny(unsafe_code)] +//! #![deny(warnings)] //! #![feature(proc_macro)] //! #![no_std] //! @@ -9,8 +10,9 @@ //! extern crate cortex_m_rtfm as rtfm; //! extern crate stm32f103xx; //! -//! use cortex_m::peripheral::SystClkSource; +//! use cortex_m::peripheral::syst::SystClkSource; //! use rtfm::{app, Threshold}; +//! use stm32f103xx::GPIOC; //! //! app! { //! device: stm32f103xx, @@ -37,31 +39,31 @@ //! //! // These are the resources this task has access to. //! // -//! // A resource can be a peripheral like `GPIOC` or a static variable -//! // like `ON` -//! resources: [GPIOC, ON], +//! // The resources listed here must also appear in `app.resources` +//! resources: [ON], //! }, //! } //! } //! -//! fn init(p: init::Peripherals, r: init::Resources) { +//! fn init(mut p: init::Peripherals, r: init::Resources) { //! // `init` can modify all the `resources` declared in `app!` //! r.ON; //! //! // power on GPIOC -//! p.RCC.apb2enr.modify(|_, w| w.iopcen().enabled()); +//! p.device.RCC.apb2enr.modify(|_, w| w.iopcen().enabled()); //! //! // configure PC13 as output -//! p.GPIOC.bsrr.write(|w| w.bs13().set()); -//! p.GPIOC +//! p.device.GPIOC.bsrr.write(|w| w.bs13().set()); +//! p.device +//! .GPIOC //! .crh //! .modify(|_, w| w.mode13().output().cnf13().push()); //! //! // configure the system timer to generate one interrupt every second -//! p.SYST.set_clock_source(SystClkSource::Core); -//! p.SYST.set_reload(8_000_000); // 1s -//! p.SYST.enable_interrupt(); -//! p.SYST.enable_counter(); +//! p.core.SYST.set_clock_source(SystClkSource::Core); +//! p.core.SYST.set_reload(8_000_000); // 1s +//! p.core.SYST.enable_interrupt(); +//! p.core.SYST.enable_counter(); //! } //! //! fn idle() -> ! { @@ -76,16 +78,23 @@ //! // //! // `r` is the set of resources this task has access to. `SYS_TICK::Resources` //! // has one field per resource declared in `app!`. -//! fn sys_tick(_t: &mut Threshold, r: SYS_TICK::Resources) { +//! #[allow(unsafe_code)] +//! fn sys_tick(_t: &mut Threshold, mut r: SYS_TICK::Resources) { //! // toggle state -//! **r.ON = !**r.ON; +//! *r.ON = !*r.ON; //! -//! if **r.ON { +//! if *r.ON { //! // set the pin PC13 high -//! r.GPIOC.bsrr.write(|w| w.bs13().set()); +//! // NOTE(unsafe) atomic write to a stateless register +//! unsafe { +//! (*GPIOC::ptr()).bsrr.write(|w| w.bs13().set()); +//! } //! } else { //! // set the pin PC13 low -//! r.GPIOC.bsrr.write(|w| w.br13().reset()); +//! // NOTE(unsafe) atomic write to a stateless register +//! unsafe { +//! (*GPIOC::ptr()).bsrr.write(|w| w.br13().reset()); +//! } //! } //! } //! ``` |