diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/cyccnt.rs | 4 | ||||
| -rw-r--r-- | src/export.rs | 4 | ||||
| -rw-r--r-- | src/lib.rs | 8 | ||||
| -rw-r--r-- | src/tq.rs | 6 |
4 files changed, 5 insertions, 17 deletions
diff --git a/src/cyccnt.rs b/src/cyccnt.rs index 6bc2ef0a..8e07b001 100644 --- a/src/cyccnt.rs +++ b/src/cyccnt.rs @@ -19,10 +19,6 @@ use crate::Fraction; /// Adding or subtracting a `Duration` of more than `(1 << 31)` cycles to an `Instant` effectively /// makes it "wrap around" and creates an incorrect value. This is also true if the operation is /// done in steps, e.g. `(instant + dur) + dur` where `dur` is `(1 << 30)` ticks. -/// -/// In multi-core contexts: this value is tied to the CYCCNT of *one* core so sending it a different -/// core makes it lose its meaning -- each Cortex-M core has its own CYCCNT counter and these are -/// usually unsynchronized and may even be running at different frequencies. #[derive(Clone, Copy, Eq, PartialEq)] pub struct Instant { inner: i32, diff --git a/src/export.rs b/src/export.rs index 8e5ef433..8a5d4e3e 100644 --- a/src/export.rs +++ b/src/export.rs @@ -28,7 +28,7 @@ where F: FnOnce(), { if priority == 1 { - // if the priority of this interrupt is `1` then BASEPRI can only be `0` + // If the priority of this interrupt is `1` then BASEPRI can only be `0` f(); unsafe { basepri::write(0) } } else { @@ -80,7 +80,7 @@ impl Priority { } } - // these two methods are used by `lock` (see below) but can't be used from the RTIC application + // These two methods are used by `lock` (see below) but can't be used from the RTIC application #[inline(always)] fn set(&self, value: u8) { self.inner.set(value) @@ -28,13 +28,6 @@ //! release. //! //! [SemVer]: https://semver.org/spec/v2.0.0.html -//! -//! # Cargo features -//! -//! - `heterogeneous`. This opt-in feature enables the *experimental* heterogeneous multi-core -//! support. This feature depends on unstable feature and requires the use of the nightly channel. -//! -//! - `homogeneous`. This opt-in feature enables the *experimental* homogeneous multi-core support. #![deny(missing_docs)] #![deny(rust_2018_compatibility)] @@ -48,7 +41,6 @@ use cortex_m::{ interrupt::Nr, peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, TPIU}, }; -#[cfg(all(not(feature = "heterogeneous"), not(feature = "homogeneous")))] use cortex_m_rt as _; // vector table pub use cortex_m_rtic_macros::app; pub use rtic_core::{Exclusive, Mutex}; @@ -40,7 +40,7 @@ where mem::transmute::<_, SYST>(()).enable_interrupt(); } - // set SysTick pending + // Set SysTick pending SCB::set_pendst(); } @@ -79,13 +79,13 @@ where }; mem::transmute::<_, SYST>(()).set_reload(dur); - // start counting down from the new reload + // Start counting down from the new reload mem::transmute::<_, SYST>(()).clear_current(); None } } else { - // the queue is empty + // The queue is empty mem::transmute::<_, SYST>(()).disable_interrupt(); None |