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path: root/macros/src/codegen/shared_resources.rs (follow)
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2023-03-01Min codegenGravatar Emil Fresk 1-5/+1
2023-03-01RTIC v2: Initial commitGravatar Emil Fresk 1-8/+10
rtic-syntax is now part of RTIC repository
2022-12-14Fix CI error caused by `critical-section` 0.2.8Gravatar Emil Fresk 1-0/+1
2022-07-27Merge #652Gravatar bors[bot] 1-4/+15
652: Remove use of basepri register on thumbv8m.base r=AfoHT a=neonquill The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error: ``` error[E0432]: unresolved import `cortex_m::register::basepri` --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5 | 25 | use cortex_m::register::basepri; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register` ``` I wasn't sure if it made more sense to replace the `armv7m` config flag with something related to basepri availability or to get closer to matching the cortex-m use of several architecture specific flags. In the end i chose to make the minimal change possible and just narrowed the existing `thumbv8m` check. Context: [cortex-m:src/register/mod.rs](https://github.com/rust-embedded/cortex-m/blob/4e908625204a1e95dd3fd5bdcd8d66d6bc11c3bc/src/register/mod.rs#L33): ``` #[cfg(all(not(armv6m), not(armv8m_base)))] pub mod basepri; ``` [cortex-m:build.rs](https://github.com/rust-embedded/cortex-m/blob/4e908625204a1e95dd3fd5bdcd8d66d6bc11c3bc/build.rs#L21): ``` } else if target.starts_with("thumbv8m.base") { println!("cargo:rustc-cfg=cortex_m"); println!("cargo:rustc-cfg=armv8m"); println!("cargo:rustc-cfg=armv8m_base"); ``` Co-authored-by: David Watson <david@neonquill.com>
2022-07-27Remove use of basepri register on thumbv8m.baseGravatar David Watson 1-4/+15
The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error: ``` error[E0432]: unresolved import `cortex_m::register::basepri` --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5 | 25 | use cortex_m::register::basepri; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register` ``` This is an attempt to account for the fact that thumbv8m.base (M23) MCUs don't have the BASEPRI register but have more than 32 interrupts. This moves away from the architecture specific config flags and switches to a more functional flag. Make the mask size depend on the max interrupt id Rather than assuming a fixed interrupt count of 32 this code uses an array of u32 bitmasks to calculate the priority mask. The size of this array is calculated at compile time based on the size of the largest interrupt id being used in the target code. For thumbv6m this should be equivalent to the previous version that used a single u32 mask. For thumbv8m.base it will be larger depending on the interrupts used. Don't write 0s to the ISER and ICER registers Writing 0s to these registers is a no-op. Since these masks should be calculated at compile time, this conditional should result in writes being optimized out of the code. Prevent panic on non-arm targets Panicking on unknown targets was breaking things like the doc build on linux. This change should only panic when building on unknown arm targets.
2022-07-27Fix missing formattingGravatar Gabriel Górski 1-2/+1
2022-07-06Allow custom `link_section` attributes for late resourcesGravatar Gabriel Górski 1-2/+9
This commit makes RTIC aware of user-provided `link_section` attributes, letting user override default section mapping.
2022-05-10Fixed warning from Rust AnalyzerGravatar Emil Fresk 1-2/+2
2022-04-20Added check for resource usage and to generate an compile error for thumbv6 ↵Gravatar Emil Fresk 1-1/+29
exceptions
2022-04-20Masks take 3Gravatar Emil Fresk 1-16/+24
2022-03-02Added support for SRP based scheduling for armv6mGravatar Per Lindgren 1-0/+33
2022-02-22Clippy with pedantic suggestionsGravatar Henrik Tjäder 1-4/+3
2021-12-25Clippy lintsGravatar Henrik Tjäder 1-1/+1
2021-11-11Better errors on when missing to lock shared resourcesGravatar Emil Fresk 1-4/+6
2021-11-03Fixed aliasing in lock implGravatar Emil Fresk 1-1/+1
2021-11-02Fixed aliasing issue due to RacyCell implementationGravatar Emil Fresk 1-1/+1
2021-08-20Use `mark_internal_name` by default for methods in `util` to make usage of ↵Gravatar datdenkikniet 1-1/+1
these functions more straightforward. fq_ident is always internal rq_ident is always internal monotonic_ident is always internal inputs_ident is always internal local_resources_ident is always internal shared_resources_ident is always internal monotonic_instants_ident is always internal tq_ident is always internal timer_queue_marker_ident is always internal static_shared_resource_ident is always internal static_local_resource_ident is always internal declared_static_local_resource_ident is always internal Only names, not idents, are now marked as internal Use same rtic internal everywhere
2021-08-19Fixed some lints from Rust Analyzer with experimental proc-macrosGravatar Emil Fresk 1-0/+1
2021-07-08Cleanup from review (needs releases to compile)Gravatar Emil Fresk 1-1/+1
2021-07-06Minimal app now compilesGravatar Emil Fresk 1-61/+23
2021-07-05Started workGravatar Emil Fresk 1-0/+145