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2022-11-14Remove unnecessary `&mut`async-2022Gravatar Emil Fresk 1-1/+1
2022-09-27Add `delay_until` a specific timeGravatar Emil Fresk 1-0/+11
2022-09-24Broke out async dispatchers into their own placeGravatar Emil Fresk 14-269/+421
2022-08-27RA fixesGravatar Emil Fresk 1-0/+3
2022-08-27Fix interrupt enum path in monotonicGravatar Emil Fresk 1-2/+2
2022-08-05Fix xtask for asyncGravatar Emil Fresk 2-9/+6
2022-08-05Fix UB in the access of `Priority` for asyc executorsGravatar Emil Fresk 2-6/+23
The `Priority` was generated on the stack in the dispatcher which caused it to be dropped after usage. This is now fixed by having the `Priority` being a static variable for executors
2022-08-05Fix codegen when having executor at multiple prioritiesGravatar Emil Fresk 3-20/+36
The codegen generated code for all executors in all dispatchers, which caused some weird bugs. Also the definition of an executor was not generated globally, this caused use after free errors when having multiple priority levels.
2022-08-03Revert async idleGravatar Emil Fresk 1-16/+4
2022-08-03async idle workingGravatar Emil Fresk 1-4/+16
2022-08-03Fix error based on retry queueGravatar Emil Fresk 1-7/+6
2022-08-03Fix styleGravatar Emil Fresk 1-1/+1
2022-08-03Added intrusive linked list for the waker queueGravatar Emil Fresk 2-81/+88
2022-08-03Fix use of parameters in async taskGravatar Emil Fresk 1-1/+1
2022-08-03Restart executor on finish if there are retriesGravatar Emil Fresk 1-8/+14
2022-08-03Example running, timeout and delay futures availableGravatar Emil Fresk 7-107/+437
2022-08-03Starting to implement async task codgenGravatar Emil Fresk 1-1/+7
2022-07-27Merge #652Gravatar bors[bot] 3-9/+26
652: Remove use of basepri register on thumbv8m.base r=AfoHT a=neonquill The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error: ``` error[E0432]: unresolved import `cortex_m::register::basepri` --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5 | 25 | use cortex_m::register::basepri; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register` ``` I wasn't sure if it made more sense to replace the `armv7m` config flag with something related to basepri availability or to get closer to matching the cortex-m use of several architecture specific flags. In the end i chose to make the minimal change possible and just narrowed the existing `thumbv8m` check. Context: [cortex-m:src/register/mod.rs](https://github.com/rust-embedded/cortex-m/blob/4e908625204a1e95dd3fd5bdcd8d66d6bc11c3bc/src/register/mod.rs#L33): ``` #[cfg(all(not(armv6m), not(armv8m_base)))] pub mod basepri; ``` [cortex-m:build.rs](https://github.com/rust-embedded/cortex-m/blob/4e908625204a1e95dd3fd5bdcd8d66d6bc11c3bc/build.rs#L21): ``` } else if target.starts_with("thumbv8m.base") { println!("cargo:rustc-cfg=cortex_m"); println!("cargo:rustc-cfg=armv8m"); println!("cargo:rustc-cfg=armv8m_base"); ``` Co-authored-by: David Watson <david@neonquill.com>
2022-07-27Remove use of basepri register on thumbv8m.baseGravatar David Watson 3-9/+26
The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error: ``` error[E0432]: unresolved import `cortex_m::register::basepri` --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5 | 25 | use cortex_m::register::basepri; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register` ``` This is an attempt to account for the fact that thumbv8m.base (M23) MCUs don't have the BASEPRI register but have more than 32 interrupts. This moves away from the architecture specific config flags and switches to a more functional flag. Make the mask size depend on the max interrupt id Rather than assuming a fixed interrupt count of 32 this code uses an array of u32 bitmasks to calculate the priority mask. The size of this array is calculated at compile time based on the size of the largest interrupt id being used in the target code. For thumbv6m this should be equivalent to the previous version that used a single u32 mask. For thumbv8m.base it will be larger depending on the interrupts used. Don't write 0s to the ISER and ICER registers Writing 0s to these registers is a no-op. Since these masks should be calculated at compile time, this conditional should result in writes being optimized out of the code. Prevent panic on non-arm targets Panicking on unknown targets was breaking things like the doc build on linux. This change should only panic when building on unknown arm targets.
2022-07-27Fix missing formattingGravatar Gabriel Górski 2-4/+2
2022-07-06Allow custom `link_section` attributes for late resourcesGravatar Gabriel Górski 2-3/+17
This commit makes RTIC aware of user-provided `link_section` attributes, letting user override default section mapping.
2022-05-24Fix clash with defmtGravatar Emil Fresk 2-4/+8
2022-05-17More ergonomic error from static asserts messagesGravatar Emil Fresk 1-3/+22
2022-05-10Fixed warning from Rust AnalyzerGravatar Emil Fresk 1-2/+2
2022-04-20Added check for resource usage and to generate an compile error for thumbv6 ↵Gravatar Emil Fresk 1-1/+29
exceptions
2022-04-20Masks take 3Gravatar Emil Fresk 2-17/+30
2022-03-02Added support for SRP based scheduling for armv6mGravatar Per Lindgren 4-3/+65
2022-02-22Clippy with pedantic suggestionsGravatar Henrik Tjäder 12-65/+64
2022-02-18rtic::mutex::prelude::* fixes glob import lintGravatar Henrik Tjäder 3-3/+3
rtic-core Mutex, Exclusive and multi-lock retained in old location to not be backwards breaking
2022-02-09Fix/mute clippy errorsGravatar Henrik Tjäder 3-20/+9
2022-01-28RTIC macro expansion: Try to find target-dirGravatar Henrik Tjäder 1-3/+63
2021-12-25Clippy lintsGravatar Henrik Tjäder 5-7/+7
2021-12-14Idle: Switch to NOP instead of WFIGravatar Henrik Tjäder 2-8/+1
Add example how to get old WFI behaviour
2021-11-25Remove #[deny(warnings)], but deny warnings for CIGravatar Henrik Tjäder 1-2/+1
2021-11-25Docs: add RTIC logoGravatar Henrik Tjäder 1-0/+5
2021-11-11Better errors on when missing to lock shared resourcesGravatar Emil Fresk 3-6/+16
2021-11-09Merge #547v0.6.0-rc.4Gravatar bors[bot] 3-31/+16
547: New monotonic trait r=AfoHT a=korken89 Co-authored-by: Emil Fresk <emil.fresk@gmail.com>
2021-11-09Merge #549v0.6.0-rc.3Gravatar bors[bot] 1-0/+4
549: fix #543 r=korken89 a=andrewgazelka The remaining PR to fix #543 alongside https://github.com/rtic-rs/rtic-syntax/pull/58 Co-authored-by: Andrew Gazelka <andrew.gazelka@gmail.com>
2021-11-09New monotonic trait workingGravatar Emil Fresk 3-31/+16
2021-11-07Match new rtic-syntax naming of shared and localGravatar Henrik Tjäder 1-2/+2
2021-11-03fix #543Gravatar Andrew Gazelka 1-0/+4
2021-11-03Fixed aliasing in lock implGravatar Emil Fresk 1-1/+1
2021-11-03Cleanup of resource initialization, no need to dereferenceGravatar Emil Fresk 1-2/+2
2021-11-02Fixed aliasing issue due to RacyCell implementationGravatar Emil Fresk 9-43/+41
2021-09-28Fix export of SYSTGravatar Emil Fresk 3-4/+3
2021-09-27Updated codegen for the updated syntax (default monotonic priority)Gravatar Emil Fresk 1-1/+5
2021-09-23The great docs updateGravatar Emil Fresk 1-0/+7
2021-09-14Merge #525Gravatar bors[bot] 2-1/+2
525: Cleanup export and actually use rtic::export, made fn init inline r=perlindgren a=korken89 Co-authored-by: Emil Fresk <emil.fresk@gmail.com>
2021-09-14Cleanup export and actually use rtic::export, made fn init inlineGravatar Emil Fresk 2-1/+2
2021-08-31style fixGravatar Jorge Aparicio 1-1/+1
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