Add fence instructions.

3 files changed, 30 insertions, 1 deletions

diff --git a/src/apic/x2apic.rs b/src/apic/x2apic.rs
index 01cc220..28d3a84 100644
--- a/src/apic/x2apic.rs
+++ b/src/apic/x2apic.rs
@@ -116,7 +116,7 @@ impl ApicControl for X2APIC {
     /// Set tsc deadline.
     fn tsc_set(&self, value: u64) {
         unsafe {
-            llvm_asm!("mfence" ::: "memory");
+            crate::fence::mfence();
             wrmsr(IA32_TSC_DEADLINE, value);
         }
     }
diff --git a/src/fence.rs b/src/fence.rs
new file mode 100644
index 0000000..9268d02
--- /dev/null
+++ b/src/fence.rs
@@ -0,0 +1,28 @@
+//! Intel fence instructions
+
+/// mfence -- Memory Fence
+///
+/// Performs a serializing operation on all load-from-memory and store-to-memory
+/// instructions that were issued prior the MFENCE instruction.
+pub fn mfence() {
+    unsafe { llvm_asm!("mfence" ::: "memory") };
+}
+
+/// sfence -- Store Fence
+///
+/// Orders processor execution relative to all memory stores prior to the SFENCE
+/// instruction. The processor ensures that every store prior to SFENCE is
+/// globally visible before any store after SFENCE becomes globally visible.
+pub fn sfence() {
+    unsafe { llvm_asm!("sfence" ::: "memory") };
+}
+
+/// lfence -- Load Fence
+///
+/// Performs a serializing operation on all load-from-memory instructions that
+/// were issued prior the LFENCE instruction. Specifically, LFENCE does not
+/// execute until all prior instructions have completed locally, and no later
+/// instruction begins execution until LFENCE completes.
+pub fn lfence() {
+    unsafe { llvm_asm!("sfence" ::: "memory") };
+}
\ No newline at end of file
diff --git a/src/lib.rs b/src/lib.rs
index 86e85e5..f31a196 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -33,6 +33,7 @@ pub mod task;
 pub mod time;
 pub mod tlb;
 pub mod vmx;
+pub mod fence;
 
 #[cfg(feature = "performance-counter")]
 pub mod perfcnt;