3 files changed, 8 insertions, 4 deletions
diff --git a/src/apic/mod.rs b/src/apic/mod.rs
index 44ef92f..c6434ea 100644
--- a/src/apic/mod.rs
+++ b/src/apic/mod.rs
@@ -145,7 +145,7 @@ pub trait ApicControl {
     fn eoi(&mut self);
 
     /// Enable TSC deadline timer.
-    fn tsc_enable(&mut self);
+    fn tsc_enable(&mut self, vector: u8);
 
     /// Set TSC deadline value.
     fn tsc_set(&self, value: u64);
diff --git a/src/apic/x2apic.rs b/src/apic/x2apic.rs
index dc99a05..e38fe9f 100644
--- a/src/apic/x2apic.rs
+++ b/src/apic/x2apic.rs
@@ -76,10 +76,10 @@ impl ApicControl for X2APIC {
     }
 
     /// Enable TSC timer
-    fn tsc_enable(&mut self) {
+    fn tsc_enable(&mut self, vector: u8) {
         unsafe {
             let mut lvt: u64 = rdmsr(IA32_X2APIC_LVT_TIMER);
-            lvt |= 0 << 17;
+            lvt &= !(1 << 17);
             lvt |= 1 << 18;
             wrmsr(IA32_X2APIC_LVT_TIMER, lvt);
         }
diff --git a/src/apic/xapic.rs b/src/apic/xapic.rs
index 3af446f..4b85580 100644
--- a/src/apic/xapic.rs
+++ b/src/apic/xapic.rs
@@ -270,8 +270,12 @@ impl ApicControl for XAPIC {
     }
 
     /// Enable TSC timer.
-    fn tsc_enable(&mut self) {
+    fn tsc_enable(&mut self, vector: u8) {
         let mut lvt: u32 = self.read(ApicRegister::XAPIC_LVT_TIMER);
+        lvt &= !0xff;
+        lvt |= vector as u32;
+        
+        lvt.set_bit(16, false);
         lvt.set_bit(17, false);
         lvt.set_bit(18, true);
         self.write(ApicRegister::XAPIC_LVT_TIMER, lvt);