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authorGravatar Sascha Wise <me@saschawise.com> 2022-02-15 19:11:50 -0800
committerGravatar Sascha Wise <me@saschawise.com> 2022-02-15 19:20:35 -0800
commit05ddb442301e617352aba697a2f9927ffc50411c (patch)
tree0f2ffa31e1152858381656021f29bf8a8ac9878c
parent8bb2a61d1cc3d2bbfd3dcc7f20fe55e9a1780df0 (diff)
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add itns field to NVIC perph
-rw-r--r--src/peripheral/nvic.rs9
1 files changed, 8 insertions, 1 deletions
diff --git a/src/peripheral/nvic.rs b/src/peripheral/nvic.rs
index 57fa94b..bd4a045 100644
--- a/src/peripheral/nvic.rs
+++ b/src/peripheral/nvic.rs
@@ -33,9 +33,16 @@ pub struct RegisterBlock {
/// Interrupt Active Bit (not present on Cortex-M0 variants)
#[cfg(not(armv6m))]
pub iabr: [RO<u32>; 16],
- #[cfg(armv6m)]
+ #[cfg(any(armv6m, armv8m))]
_reserved4: [u32; 16],
+ #[cfg(armv8m)]
+ /// Interrupt Target Non-secure (only present on Arm v8-M)
+ pub itns: [RW<u32>; 16],
+ #[cfg(armv8m)]
+ _reserved5: [u32; 32],
+
+ #[cfg(not(armv8m))]
_reserved5: [u32; 48],
/// Interrupt Priority