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author | 2018-05-09 13:55:38 +0200 | |
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committer | 2018-05-15 13:59:49 +0200 | |
commit | 14c5e9049f8b0a95d98517fe2f121777175f2286 (patch) | |
tree | bccda86409c1906013627709853abb9ca2069fa0 | |
parent | f63d0c0114e50538cd65a18c2f2e1b1d6dcd5e8f (diff) | |
download | cortex-m-14c5e9049f8b0a95d98517fe2f121777175f2286.tar.gz cortex-m-14c5e9049f8b0a95d98517fe2f121777175f2286.tar.zst cortex-m-14c5e9049f8b0a95d98517fe2f121777175f2286.zip |
Add methods to control SLEEPDEEP bit
Close #68
-rw-r--r-- | src/peripheral/scb.rs | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs index 58e083b..2ad0770 100644 --- a/src/peripheral/scb.rs +++ b/src/peripheral/scb.rs @@ -580,3 +580,21 @@ impl SCB { ::asm::isb(); } } + +const SCB_SCR_SLEEPDEEP: u32 = 0x1 << 2; + +impl SCB { + /// Set the SLEEPDEEP bit in the SCR register + pub fn set_sleepdeep(&mut self) { + unsafe { + self.scr.modify(|scr| scr | SCB_SCR_SLEEPDEEP); + } + } + + /// Clear the SLEEPDEEP bit in the SCR register + pub fn clear_sleepdeep(&mut self) { + unsafe { + self.scr.modify(|scr| scr & !SCB_SCR_SLEEPDEEP); + } + } +} |