Merge #160

160: Update for 2018 edition r=korken89 a=adamgreig



Co-authored-by: Adam Greig <adam@adamgreig.com>

17 files changed, 62 insertions, 76 deletions

diff --git a/CHANGELOG.md b/CHANGELOG.md
index cf1e370..8941709 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -302,10 +302,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 #![feature(used)]
 #![no_std]
 
-extern crate cortex_m;
-extern crate cortex_m_rt;
-extern crate stm32f30x;
-
 use core::cell::RefCell;
 
 use cortex_m::ctxt::Local;
diff --git a/Cargo.toml b/Cargo.toml
index 8e59091..4f1e860 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -12,6 +12,7 @@ name = "cortex-m"
 readme = "README.md"
 repository = "https://github.com/japaric/cortex-m"
 version = "0.6.0"
+edition = "2018"
 links = "cortex-m"  # prevent multiple versions of this crate to be linked together
 
 [dependencies]
diff --git a/src/interrupt.rs b/src/interrupt.rs
index b57cc80..58f552a 100644
--- a/src/interrupt.rs
+++ b/src/interrupt.rs
@@ -61,7 +61,7 @@ pub fn free<F, R>(f: F) -> R
 where
     F: FnOnce(&CriticalSection) -> R,
 {
-    let primask = ::register::primask::read();
+    let primask = crate::register::primask::read();
 
     // disable interrupts
     disable();
diff --git a/src/itm.rs b/src/itm.rs
index 4f8dcf8..6e936d8 100644
--- a/src/itm.rs
+++ b/src/itm.rs
@@ -6,7 +6,7 @@ use core::{fmt, mem, ptr, slice};
 
 use aligned::{Aligned, A4};
 
-use peripheral::itm::Stim;
+use crate::peripheral::itm::Stim;
 
 // NOTE assumes that `bytes` is 32-bit aligned
 unsafe fn write_words(stim: &mut Stim, bytes: &[u32]) {
diff --git a/src/lib.rs b/src/lib.rs
index 90711bf..9d8171e 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -47,4 +47,4 @@ pub mod itm;
 pub mod peripheral;
 pub mod register;
 
-pub use peripheral::Peripherals;
+pub use crate::peripheral::Peripherals;
diff --git a/src/macros.rs b/src/macros.rs
index 813552f..6b3b269 100644
--- a/src/macros.rs
+++ b/src/macros.rs
@@ -33,8 +33,7 @@ macro_rules! iprintln {
 /// # Example
 ///
 /// ``` no_run
-/// #[macro_use(singleton)]
-/// extern crate cortex_m;
+/// use cortex_m::singleton;
 ///
 /// fn main() {
 ///     // OK if `main` is executed only once
@@ -77,8 +76,7 @@ macro_rules! singleton {
 }
 
 /// ``` compile_fail
-/// #[macro_use(singleton)]
-/// extern crate cortex_m;
+/// use cortex_m::singleton;
 ///
 /// fn main() {}
 ///
@@ -92,8 +90,7 @@ const CFAIL: () = ();
 
 /// ```
 /// #![deny(unsafe_code)]
-/// #[macro_use(singleton)]
-/// extern crate cortex_m;
+/// use cortex_m::singleton;
 ///
 /// fn main() {}
 ///
diff --git a/src/peripheral/cbp.rs b/src/peripheral/cbp.rs
index 2535d0b..8c05217 100644
--- a/src/peripheral/cbp.rs
+++ b/src/peripheral/cbp.rs
@@ -4,7 +4,7 @@
 
 use volatile_register::WO;
 
-use peripheral::CBP;
+use crate::peripheral::CBP;
 
 /// Register block
 #[repr(C)]
diff --git a/src/peripheral/cpuid.rs b/src/peripheral/cpuid.rs
index c79ad18..7b86ddc 100644
--- a/src/peripheral/cpuid.rs
+++ b/src/peripheral/cpuid.rs
@@ -5,7 +5,7 @@ use volatile_register::RO;
 use volatile_register::RW;
 
 #[cfg(not(armv6m))]
-use peripheral::CPUID;
+use crate::peripheral::CPUID;
 
 /// Register block
 #[repr(C)]
@@ -104,7 +104,7 @@ impl CPUID {
         const CCSIDR_ASSOCIATIVITY_MASK: u32 = 0x3FF << CCSIDR_ASSOCIATIVITY_POS;
 
         self.select_cache(level, ind);
-        ::asm::dsb();
+        crate::asm::dsb();
         let ccsidr = self.ccsidr.read();
         (
             (1 + ((ccsidr & CCSIDR_NUMSETS_MASK) >> CCSIDR_NUMSETS_POS)) as u16,
diff --git a/src/peripheral/dcb.rs b/src/peripheral/dcb.rs
index e12542c..f3b4bc2 100644
--- a/src/peripheral/dcb.rs
+++ b/src/peripheral/dcb.rs
@@ -3,7 +3,7 @@
 use volatile_register::{RW, WO};
 
 use core::ptr;
-use peripheral::DCB;
+use crate::peripheral::DCB;
 
 const DCB_DEMCR_TRCENA: u32 = 1 << 24;
 
diff --git a/src/peripheral/dwt.rs b/src/peripheral/dwt.rs
index 77ec450..5fc59f3 100644
--- a/src/peripheral/dwt.rs
+++ b/src/peripheral/dwt.rs
@@ -4,7 +4,7 @@
 use volatile_register::WO;
 use volatile_register::{RO, RW};
 
-use peripheral::DWT;
+use crate::peripheral::DWT;
 
 /// Register block
 #[repr(C)]
diff --git a/src/peripheral/mod.rs b/src/peripheral/mod.rs
index 8d2bd3f..7019224 100644
--- a/src/peripheral/mod.rs
+++ b/src/peripheral/mod.rs
@@ -8,8 +8,6 @@
 //! the [`Peripherals::take`](struct.Peripherals.html#method.take) method.
 //!
 //! ``` no_run
-//! extern crate cortex_m;
-//!
 //! use cortex_m::peripheral::Peripherals;
 //!
 //! fn main() {
@@ -22,8 +20,6 @@
 //! `Option`. Subsequent calls to the method will result in a `None` value being returned.
 //!
 //! ``` no_run
-//! extern crate cortex_m;
-//!
 //! use cortex_m::peripheral::Peripherals;
 //!
 //! fn main() {
@@ -36,8 +32,6 @@
 //! [`DWT::get_cycle_count`](struct.DWT.html#method.get_cycle_count) method.
 //!
 //! ``` no_run
-//! extern crate cortex_m;
-//!
 //! use cortex_m::peripheral::{DWT, Peripherals};
 //!
 //! fn main() {
@@ -56,8 +50,6 @@
 //! safe higher level abstractions.
 //!
 //! ``` no_run
-//! extern crate cortex_m;
-//!
 //! use cortex_m::peripheral::{DWT, Peripherals};
 //!
 //! fn main() {
@@ -81,7 +73,7 @@
 use core::marker::PhantomData;
 use core::ops;
 
-use interrupt;
+use crate::interrupt;
 
 #[cfg(not(armv6m))]
 pub mod cbp;
diff --git a/src/peripheral/nvic.rs b/src/peripheral/nvic.rs
index d123b7d..c9dae7f 100644
--- a/src/peripheral/nvic.rs
+++ b/src/peripheral/nvic.rs
@@ -4,8 +4,8 @@ use volatile_register::RW;
 #[cfg(not(armv6m))]
 use volatile_register::{RO, WO};
 
-use interrupt::Nr;
-use peripheral::NVIC;
+use crate::interrupt::Nr;
+use crate::peripheral::NVIC;
 
 /// Register block
 #[repr(C)]
diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs
index e3f3884..f4dfa52 100644
--- a/src/peripheral/scb.rs
+++ b/src/peripheral/scb.rs
@@ -321,8 +321,8 @@ impl SCB {
         // Enable I-Cache
         unsafe { self.ccr.modify(|r| r | SCB_CCR_IC_MASK) };
 
-        ::asm::dsb();
-        ::asm::isb();
+        crate::asm::dsb();
+        crate::asm::isb();
     }
 
     /// Disables I-Cache if currently enabled
@@ -342,15 +342,15 @@ impl SCB {
         // Invalidate I-Cache
         cbp.iciallu();
 
-        ::asm::dsb();
-        ::asm::isb();
+        crate::asm::dsb();
+        crate::asm::isb();
     }
 
     /// Returns whether the I-Cache is currently enabled
     #[inline]
     pub fn icache_enabled() -> bool {
-        ::asm::dsb();
-        ::asm::isb();
+        crate::asm::dsb();
+        crate::asm::isb();
 
         // NOTE(unsafe) atomic read with no side effects
         unsafe { (*Self::ptr()).ccr.read() & SCB_CCR_IC_MASK == SCB_CCR_IC_MASK }
@@ -365,8 +365,8 @@ impl SCB {
         // Invalidate I-Cache
         cbp.iciallu();
 
-        ::asm::dsb();
-        ::asm::isb();
+        crate::asm::dsb();
+        crate::asm::isb();
     }
 
     /// Enables D-cache if currently disabled
@@ -383,8 +383,8 @@ impl SCB {
         // Now turn on the DCache
         unsafe { self.ccr.modify(|r| r | SCB_CCR_DC_MASK) };
 
-        ::asm::dsb();
-        ::asm::isb();
+        crate::asm::dsb();
+        crate::asm::isb();
     }
 
     /// Disables D-cache if currently enabled
@@ -405,8 +405,8 @@ impl SCB {
     /// Returns whether the D-Cache is currently enabled
     #[inline]
     pub fn dcache_enabled() -> bool {
-        ::asm::dsb();
-        ::asm::isb();
+        crate::asm::dsb();
+        crate::asm::isb();
 
         // NOTE(unsafe) atomic read with no side effects
         unsafe { (*Self::ptr()).ccr.read() & SCB_CCR_DC_MASK == SCB_CCR_DC_MASK }
@@ -432,8 +432,8 @@ impl SCB {
             }
         }
 
-        ::asm::dsb();
-        ::asm::isb();
+        crate::asm::dsb();
+        crate::asm::isb();
     }
 
     /// Cleans D-cache
@@ -451,8 +451,8 @@ impl SCB {
             }
         }
 
-        ::asm::dsb();
-        ::asm::isb();
+        crate::asm::dsb();
+        crate::asm::isb();
     }
 
     /// Cleans and invalidates D-cache
@@ -470,8 +470,8 @@ impl SCB {
             }
         }
 
-        ::asm::dsb();
-        ::asm::isb();
+        crate::asm::dsb();
+        crate::asm::isb();
     }
 
     /// Invalidates D-cache by address
@@ -491,7 +491,7 @@ impl SCB {
         // NOTE(unsafe) All CBP registers are write-only and stateless
         let mut cbp = unsafe { CBP::new() };
 
-        ::asm::dsb();
+        crate::asm::dsb();
 
         // Cache lines are fixed to 32 bit on Cortex-M7 and not present in earlier Cortex-M
         const LINESIZE: usize = 32;
@@ -504,8 +504,8 @@ impl SCB {
             addr += LINESIZE;
         }
 
-        ::asm::dsb();
-        ::asm::isb();
+        crate::asm::dsb();
+        crate::asm::isb();
     }
 
     /// Cleans D-cache by address
@@ -525,7 +525,7 @@ impl SCB {
         // NOTE(unsafe) All CBP registers are write-only and stateless
         let mut cbp = unsafe { CBP::new() };
 
-        ::asm::dsb();
+        crate::asm::dsb();
 
         // Cache lines are fixed to 32 bit on Cortex-M7 and not present in earlier Cortex-M
         const LINESIZE: usize = 32;
@@ -538,8 +538,8 @@ impl SCB {
             addr += LINESIZE;
         }
 
-        ::asm::dsb();
-        ::asm::isb();
+        crate::asm::dsb();
+        crate::asm::isb();
     }
 
     /// Cleans and invalidates D-cache by address
@@ -560,7 +560,7 @@ impl SCB {
         // NOTE(unsafe) All CBP registers are write-only and stateless
         let mut cbp = unsafe { CBP::new() };
 
-        ::asm::dsb();
+        crate::asm::dsb();
 
         // Cache lines are fixed to 32 bit on Cortex-M7 and not present in earlier Cortex-M
         const LINESIZE: usize = 32;
@@ -573,8 +573,8 @@ impl SCB {
             addr += LINESIZE;
         }
 
-        ::asm::dsb();
-        ::asm::isb();
+        crate::asm::dsb();
+        crate::asm::isb();
     }
 }
 
@@ -622,7 +622,7 @@ impl SCB {
     /// Initiate a system reset request to reset the MCU
     #[deprecated(since = "0.6.1", note = "Use `SCB::sys_reset`")]
     pub fn system_reset(&mut self) -> ! {
-        ::asm::dsb();
+        crate::asm::dsb();
         unsafe {
             self.aircr.modify(
                 |r| {
@@ -632,16 +632,16 @@ impl SCB {
                 }, // set the bit
             )
         };
-        ::asm::dsb();
+        crate::asm::dsb();
         loop {
             // wait for the reset
-            ::asm::nop(); // avoid rust-lang/rust#28728
+            crate::asm::nop(); // avoid rust-lang/rust#28728
         }
     }
 
     /// Initiate a system reset request to reset the MCU
     pub fn sys_reset() -> ! {
-        ::asm::dsb();
+        crate::asm::dsb();
         unsafe {
             (*Self::ptr()).aircr.modify(
                 |r| {
@@ -651,10 +651,10 @@ impl SCB {
                 }, // set the bit
             )
         };
-        ::asm::dsb();
+        crate::asm::dsb();
         loop {
             // wait for the reset
-            ::asm::nop(); // avoid rust-lang/rust#28728
+            crate::asm::nop(); // avoid rust-lang/rust#28728
         }
     }
 }
diff --git a/src/peripheral/syst.rs b/src/peripheral/syst.rs
index c1e9710..1e94a1d 100644
--- a/src/peripheral/syst.rs
+++ b/src/peripheral/syst.rs
@@ -2,7 +2,7 @@
 
 use volatile_register::{RO, RW};
 
-use peripheral::SYST;
+use crate::peripheral::SYST;
 
 /// Register block
 #[repr(C)]
diff --git a/src/peripheral/test.rs b/src/peripheral/test.rs
index 4eb48f5..5446a71 100644
--- a/src/peripheral/test.rs
+++ b/src/peripheral/test.rs
@@ -1,6 +1,6 @@
 #[test]
 fn cpuid() {
-    let cpuid = unsafe { &*::peripheral::CPUID::ptr() };
+    let cpuid = unsafe { &*crate::peripheral::CPUID::ptr() };
 
     assert_eq!(address(&cpuid.base), 0xE000_ED00);
     assert_eq!(address(&cpuid.pfr), 0xE000_ED40);
@@ -16,7 +16,7 @@ fn cpuid() {
 
 #[test]
 fn dcb() {
-    let dcb = unsafe { &*::peripheral::DCB::ptr() };
+    let dcb = unsafe { &*crate::peripheral::DCB::ptr() };
 
     assert_eq!(address(&dcb.dhcsr), 0xE000_EDF0);
     assert_eq!(address(&dcb.dcrsr), 0xE000_EDF4);
@@ -26,7 +26,7 @@ fn dcb() {
 
 #[test]
 fn dwt() {
-    let dwt = unsafe { &*::peripheral::DWT::ptr() };
+    let dwt = unsafe { &*crate::peripheral::DWT::ptr() };
 
     assert_eq!(address(&dwt.ctrl), 0xE000_1000);
     #[cfg(not(armv6m))]
@@ -56,7 +56,7 @@ fn dwt() {
 
 #[test]
 fn fpb() {
-    let fpb = unsafe { &*::peripheral::FPB::ptr() };
+    let fpb = unsafe { &*crate::peripheral::FPB::ptr() };
 
     assert_eq!(address(&fpb.ctrl), 0xE000_2000);
     assert_eq!(address(&fpb.remap), 0xE000_2004);
@@ -68,7 +68,7 @@ fn fpb() {
 
 #[test]
 fn fpu() {
-    let fpu = unsafe { &*::peripheral::FPU::ptr() };
+    let fpu = unsafe { &*crate::peripheral::FPU::ptr() };
 
     assert_eq!(address(&fpu.fpccr), 0xE000_EF34);
     assert_eq!(address(&fpu.fpcar), 0xE000_EF38);
@@ -80,7 +80,7 @@ fn fpu() {
 
 #[test]
 fn itm() {
-    let itm = unsafe { &*::peripheral::ITM::ptr() };
+    let itm = unsafe { &*crate::peripheral::ITM::ptr() };
 
     assert_eq!(address(&itm.stim), 0xE000_0000);
     assert_eq!(address(&itm.ter), 0xE000_0E00);
@@ -92,7 +92,7 @@ fn itm() {
 
 #[test]
 fn mpu() {
-    let mpu = unsafe { &*::peripheral::MPU::ptr() };
+    let mpu = unsafe { &*crate::peripheral::MPU::ptr() };
 
     assert_eq!(address(&mpu._type), 0xE000ED90);
     assert_eq!(address(&mpu.ctrl), 0xE000ED94);
@@ -109,7 +109,7 @@ fn mpu() {
 
 #[test]
 fn nvic() {
-    let nvic = unsafe { &*::peripheral::NVIC::ptr() };
+    let nvic = unsafe { &*crate::peripheral::NVIC::ptr() };
 
     assert_eq!(address(&nvic.iser), 0xE000E100);
     assert_eq!(address(&nvic.icer), 0xE000E180);
@@ -123,7 +123,7 @@ fn nvic() {
 
 #[test]
 fn scb() {
-    let scb = unsafe { &*::peripheral::SCB::ptr() };
+    let scb = unsafe { &*crate::peripheral::SCB::ptr() };
 
     assert_eq!(address(&scb.icsr), 0xE000_ED04);
     assert_eq!(address(&scb.vtor), 0xE000_ED08);
@@ -143,7 +143,7 @@ fn scb() {
 
 #[test]
 fn syst() {
-    let syst = unsafe { &*::peripheral::SYST::ptr() };
+    let syst = unsafe { &*crate::peripheral::SYST::ptr() };
 
     assert_eq!(address(&syst.csr), 0xE000_E010);
     assert_eq!(address(&syst.rvr), 0xE000_E014);
@@ -153,7 +153,7 @@ fn syst() {
 
 #[test]
 fn tpiu() {
-    let tpiu = unsafe { &*::peripheral::TPIU::ptr() };
+    let tpiu = unsafe { &*crate::peripheral::TPIU::ptr() };
 
     assert_eq!(address(&tpiu.sspsr), 0xE004_0000);
     assert_eq!(address(&tpiu.cspsr), 0xE004_0004);
diff --git a/src/register/basepri.rs b/src/register/basepri.rs
index a9cd6ef..a09e34b 100644
--- a/src/register/basepri.rs
+++ b/src/register/basepri.rs
@@ -39,7 +39,7 @@ pub unsafe fn write(_basepri: u8) {
             #[cfg(not(feature = "cm7-r0p1"))]
             () => asm!("msr BASEPRI, $0" :: "r"(_basepri) : "memory" : "volatile"),
             #[cfg(feature = "cm7-r0p1")]
-            () => ::interrupt::free(
+            () => crate::interrupt::free(
                 |_| asm!("msr BASEPRI, $0" :: "r"(_basepri) : "memory" : "volatile"),
             ),
         },
diff --git a/src/register/basepri_max.rs b/src/register/basepri_max.rs
index 59ddb44..694fd75 100644
--- a/src/register/basepri_max.rs
+++ b/src/register/basepri_max.rs
@@ -16,7 +16,7 @@ pub fn write(_basepri: u8) {
                 #[cfg(not(feature = "cm7-r0p1"))]
                 () => asm!("msr BASEPRI_MAX, $0" :: "r"(_basepri) : "memory" : "volatile"),
                 #[cfg(feature = "cm7-r0p1")]
-                () => ::interrupt::free(
+                () => crate::interrupt::free(
                     |_| asm!("msr BASEPRI_MAX, $0" :: "r"(_basepri) : "memory" : "volatile"),
                 ),
             }