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| author |  qwerty19106 <qwerty19106@gmail.com>
| 2018-10-01 12:20:34 +0400 |
|---|---|---|
| committer | qwerty19106 <qwerty19106@gmail.com>
| 2018-10-01 12:20:34 +0400 |
| commit | 2cb6f4ba35b40337d6406acf5b565ccd0fb652c0 (patch) | |
| tree | 2ca71df33c77a5a431381ac53168add2d9725ee0 | |
| parent | fac7e856f75e5ceff87d2e1107ffd683117f6e15 (diff) | |
| download | cortex-m-2cb6f4ba35b40337d6406acf5b565ccd0fb652c0.tar.gz cortex-m-2cb6f4ba35b40337d6406acf5b565ccd0fb652c0.tar.zst cortex-m-2cb6f4ba35b40337d6406acf5b565ccd0fb652c0.zip | |
Autoformat scb.rs by rustfmt
| -rw-r--r-- | src/peripheral/scb.rs | 27 |
1 files changed, 14 insertions, 13 deletions
diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs index 14eaa69..e773c9c 100644 --- a/src/peripheral/scb.rs +++ b/src/peripheral/scb.rs @@ -7,9 +7,9 @@ use volatile_register::RW; #[cfg(not(armv6m))] use super::cpuid::CsselrCacheType; #[cfg(not(armv6m))] -use super::CPUID; -#[cfg(not(armv6m))] use super::CBP; +#[cfg(not(armv6m))] +use super::CPUID; use super::SCB; /// Register block @@ -604,13 +604,18 @@ impl SCB { /// Initiate a system reset request to reset the MCU pub fn system_reset(&mut self) -> ! { ::asm::dsb(); - unsafe { self.aircr.modify(|r| - SCB_AIRCR_VECTKEY | // otherwise the write is ignored + unsafe { + self.aircr.modify( + |r| { + SCB_AIRCR_VECTKEY | // otherwise the write is ignored r & SCB_AIRCR_PRIGROUP_MASK | // keep priority group unchanged - SCB_AIRCR_SYSRESETREQ // set the bit - ) }; + SCB_AIRCR_SYSRESETREQ + }, // set the bit + ) + }; ::asm::dsb(); - loop { // wait for the reset + loop { + // wait for the reset ::asm::nop(); // avoid rust-lang/rust#28728 } } @@ -632,9 +637,7 @@ impl SCB { /// Check if PENDSVSET bit in the ICSR register is set meaning PendSV interrupt is pending pub fn is_pendsv_pending() -> bool { - unsafe { - (*Self::ptr()).icsr.read() & SCB_ICSR_PENDSVSET == SCB_ICSR_PENDSVSET - } + unsafe { (*Self::ptr()).icsr.read() & SCB_ICSR_PENDSVSET == SCB_ICSR_PENDSVSET } } /// Set the PENDSVCLR bit in the ICSR register which will clear a pending PendSV interrupt @@ -655,9 +658,7 @@ impl SCB { /// Check if PENDSTSET bit in the ICSR register is set meaning SysTick interrupt is pending #[inline] pub fn is_pendst_pending() -> bool { - unsafe { - (*Self::ptr()).icsr.read() & SCB_ICSR_PENDSTSET == SCB_ICSR_PENDSTSET - } + unsafe { (*Self::ptr()).icsr.read() & SCB_ICSR_PENDSTSET == SCB_ICSR_PENDSTSET } } /// Set the PENDSTCLR bit in the ICSR register which will clear a pending SysTick interrupt |