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authorGravatar Jorge Aparicio <japaricious@gmail.com> 2017-04-11 22:22:13 -0500
committerGravatar Jorge Aparicio <japaricious@gmail.com> 2017-04-11 22:22:13 -0500
commit5531a594d3564c94734d36b067fa7bb4c4cb0bd6 (patch)
tree2445e1c74ada5fa2079e2871c75cd347e41ed64c
parente5fd02bd1c13bec4cc2e170f382000737857fcfc (diff)
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remove the, now unnecessary, unsafe blocks
-rw-r--r--src/peripheral/mod.rs2
-rw-r--r--src/register/basepri.rs12
2 files changed, 6 insertions, 8 deletions
diff --git a/src/peripheral/mod.rs b/src/peripheral/mod.rs
index d14d782..78ddfdb 100644
--- a/src/peripheral/mod.rs
+++ b/src/peripheral/mod.rs
@@ -386,7 +386,7 @@ impl Nvic {
{
let nr = interrupt.nr();
- unsafe { self.ipr[usize::from(nr)].write(prio) }
+ self.ipr[usize::from(nr)].write(prio)
}
}
diff --git a/src/register/basepri.rs b/src/register/basepri.rs
index d5ec002..ca461e8 100644
--- a/src/register/basepri.rs
+++ b/src/register/basepri.rs
@@ -17,11 +17,9 @@ pub fn read() -> u8 {
/// Writes to the CPU register
#[inline(always)]
pub unsafe fn write(basepri: u8) {
- unsafe {
- asm!("msr BASEPRI, $0"
- :
- : "r"(basepri)
- :
- : "volatile");
- }
+ asm!("msr BASEPRI, $0"
+ :
+ : "r"(basepri)
+ :
+ : "volatile");
}