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author | 2020-09-05 18:43:19 +0100 | |
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committer | 2020-09-05 18:43:19 +0100 | |
commit | 5d5e15181f4d4eeacb9876a514f7359527f9b361 (patch) | |
tree | e31483e976501da4bab32c76e18340c66b888a54 | |
parent | 78d78149e1f7fa5a9b2244453cebd5bc5c5bb2c8 (diff) | |
download | cortex-m-5d5e15181f4d4eeacb9876a514f7359527f9b361.tar.gz cortex-m-5d5e15181f4d4eeacb9876a514f7359527f9b361.tar.zst cortex-m-5d5e15181f4d4eeacb9876a514f7359527f9b361.zip |
Address review comments
-rw-r--r-- | CHANGELOG.md | 9 | ||||
-rw-r--r-- | asm/inline.rs | 14 |
2 files changed, 18 insertions, 5 deletions
diff --git a/CHANGELOG.md b/CHANGELOG.md index 4b5a837..f5695d4 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -15,6 +15,15 @@ and this project adheres to [Semantic Versioning](http://semver.org/). eventually replace the existing `ptr()` API. - A delay driver based on SysTick. +### Changed + +- Previously, asm calls without the `inline-asm` feature enabled used pre-built + objects which were built by a GCC compiler, while `inline-asm` enabled the + use of `llvm_asm!` calls. The asm system has been replaced with a new + technique which generates Rust static libs for stable calling, and uses the + new `asm!` macro with `inline-asm`. See the `asm/lib.rs` documentation for + more details. + ## [v0.6.3] - 2020-07-20 ### Added diff --git a/asm/inline.rs b/asm/inline.rs index 67fa70e..3fbba92 100644 --- a/asm/inline.rs +++ b/asm/inline.rs @@ -24,9 +24,13 @@ pub unsafe fn __control_r() -> u32 { pub unsafe fn __control_w(w: u32) { // ISB is required after writing to CONTROL, // per ARM architectural requirements (see Application Note 321). - asm!("msr CONTROL, {}", "isb", in(reg) w); + asm!( + "msr CONTROL, {}", + "isb", + in(reg) w + ); - // Ensure instructions are not reordered around the CONTROL update. + // Ensure memory accesses are not reordered around the CONTROL update. compiler_fence(Ordering::SeqCst); } @@ -34,13 +38,13 @@ pub unsafe fn __control_w(w: u32) { pub unsafe fn __cpsid() { asm!("cpsid i"); - // Ensure no subsequent instructions are reordered to before interrupts are disabled. + // Ensure no subsequent memory accesses are reordered to before interrupts are disabled. compiler_fence(Ordering::SeqCst); } #[inline(always)] pub unsafe fn __cpsie() { - // Ensure no preceeding instructions are reordered to after interrupts are enabled. + // Ensure no preceeding memory accesses are reordered to after interrupts are enabled. compiler_fence(Ordering::SeqCst); asm!("cpsie i"); @@ -61,7 +65,7 @@ pub unsafe fn __delay(cyc: u32) { #[inline(always)] pub unsafe fn __dmb() { asm!("dmb"); - compiler_fence(Ordering::AcqRel); + compiler_fence(Ordering::SeqCst); } #[inline(always)] |