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| author |  bors[bot] <26634292+bors[bot]@users.noreply.github.com>
| 2022-01-02 15:49:08 +0000 |
|---|---|---|
| committer |  GitHub <noreply@github.com>
| 2022-01-02 15:49:08 +0000 |
| commit | 78f4945d33eab255861c36f856ead9b09edfb022 (patch) | |
| tree | fb1af0ff378d513c87d0cd79227839eef3ed8885 | |
| parent | bef6ed1819cedfb38e23396f9a99566dc23e2829 (diff) | |
| parent | 5eb38fea126ddefc635e0b29a05687e47218aac9 (diff) | |
| download | cortex-m-78f4945d33eab255861c36f856ead9b09edfb022.tar.gz cortex-m-78f4945d33eab255861c36f856ead9b09edfb022.tar.zst cortex-m-78f4945d33eab255861c36f856ead9b09edfb022.zip | |
Merge #378
378: CHANGELOG: add missing items r=adamgreig a=tmplt
Co-authored-by: Viktor Vilhelm Sonesten <v@tmplt.dev>
| -rw-r--r-- | CHANGELOG.md | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/CHANGELOG.md b/CHANGELOG.md index 7da0459..8f3ad1e 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -18,10 +18,13 @@ and this project adheres to [Semantic Versioning](http://semver.org/). There is a feature `cm7` to enable access to these. - Added `delay::Delay::with_source`, a constructor that lets you specify the SysTick clock source (#374). -- Added the capability for `DWT` to do cycle count comparison (#367). - Updated `SCB.ICSR.VECTACTIVE`/`SCB::vect_active()` to be 9 bits instead of 8. Also fixes `VectActive::from` to take a `u16` and subtract `16` for `VectActive::Interrupt`s to match `SBC::vect_active()` (#373). +- DWT: add `configure` API for address, cycle count comparison (#342, #367). +- ITM: add `configure` API (#342). +- TPIU: add API for *Formatter and Flush Control* (FFCR) and *Selected Pin Control* (SPPR) registers (#342). +- Add `std` and `serde` crate features for improved host-side ITM decode functionality when working with the downstream `itm`, `cargo-rtic-scope` crates (#363, #366). ### Deprecated |