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| author |  Garret Kelly <gdk@google.com>
| 2018-08-08 12:27:36 -0400 |
|---|---|---|
| committer | Garret Kelly <gdk@google.com>
| 2018-08-08 12:27:36 -0400 |
| commit | 88726d96316e9ab6f71a14619e02ed33478f585b (patch) | |
| tree | 4a54c8ce96c11543e2705766ec4dafeac5ecbf8b | |
| parent | 13b87923deed801adb3f6412efa2c05dc43304c4 (diff) | |
| download | cortex-m-88726d96316e9ab6f71a14619e02ed33478f585b.tar.gz cortex-m-88726d96316e9ab6f71a14619e02ed33478f585b.tar.zst cortex-m-88726d96316e9ab6f71a14619e02ed33478f585b.zip | |
Always expose the VTOR register (#100)
Cortex-M0+ platforms had the VTOR register hidden because of the way the
SCB chose to expose it. This change exposes it on all platforms, with
the side effect that it will be visible on Cortex-M0 even thought the M0
SCB does not define it.
| -rw-r--r-- | src/peripheral/scb.rs | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs index 569ec6a..d26e0a6 100644 --- a/src/peripheral/scb.rs +++ b/src/peripheral/scb.rs @@ -19,10 +19,7 @@ pub struct RegisterBlock { pub icsr: RW<u32>, /// Vector Table Offset (not present on Cortex-M0 variants) - #[cfg(not(armv6m))] pub vtor: RW<u32>, - #[cfg(armv6m)] - _reserved0: u32, /// Application Interrupt and Reset Control pub aircr: RW<u32>, |