Merge #111

111: Add DCB::enable_trace() and DCB::disable_trace() r=korken89 a=kellerkindt

This is required for the cycle counter of DWT to work, if the power supply has been unplugged since the last time it has been flashed japaric/stm32f103xx-hal/issues/76.
See bit 24 here http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/CEGHJDCF.html

Corresponding PR in stm32f103xx-hal: japaric/stm32f103xx-hal/pull/94

Co-authored-by: kellerkindt <michael@kellerkindt.com>
Co-authored-by: Michael Watzko <michael@watzko.de>

1 files changed, 21 insertions, 0 deletions

diff --git a/src/peripheral/dcb.rs b/src/peripheral/dcb.rs
index 02ec901..14dc75b 100644
--- a/src/peripheral/dcb.rs
+++ b/src/peripheral/dcb.rs
@@ -2,6 +2,10 @@
 
 use volatile_register::{RW, WO};
 
+use peripheral::DCB;
+
+const DCB_DEMCR_TRCENA: u32 = 1 << 24;
+
 /// Register block
 #[repr(C)]
 pub struct RegisterBlock {
@@ -14,3 +18,20 @@ pub struct RegisterBlock {
     /// Debug Exception and Monitor Control
     pub demcr: RW<u32>,
 }
+
+impl DCB {
+    /// Enables TRACE. This is for example required by the 
+    /// `peripheral::DWT` cycle counter to work properly.
+    /// As by STM documentation, this flag is not reset on
+    /// soft-reset, only on power reset.
+    pub fn enable_trace(&mut self) {
+        // set bit 24 / TRCENA
+        unsafe { self.demcr.modify(|w| w | DCB_DEMCR_TRCENA); }
+    }
+    
+    /// Disables TRACE. See `DCB::enable_trace()` for more details
+    pub fn disable_trace(&mut self) {
+        // unset bit 24 / TRCENA
+        unsafe { self.demcr.modify(|w| w & !DCB_DEMCR_TRCENA); }
+    }
+}